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[Sparc] Add support for parsing branches and conditional move instructions with %fcc1-%fcc3 conditional registers.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202616 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju
2014-03-02 06:28:15 +00:00
parent 18fe44cb05
commit a21b315a06
5 changed files with 156 additions and 86 deletions
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11
lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
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@@ -146,11 +146,12 @@ void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum,
case SP::BPFCCA:
case SP::BPFCCNT:
case SP::BPFCCANT:
case SP::MOVFCCrr:
case SP::MOVFCCri:
case SP::FMOVS_FCC:
case SP::FMOVD_FCC:
case SP::FMOVQ_FCC: // Make sure CC is a fp conditional flag.
case SP::MOVFCCrr: case SP::V9MOVFCCrr:
case SP::MOVFCCri: case SP::V9MOVFCCri:
case SP::FMOVS_FCC: case SP::V9FMOVS_FCC:
case SP::FMOVD_FCC: case SP::V9FMOVD_FCC:
case SP::FMOVQ_FCC: case SP::V9FMOVQ_FCC:
// Make sure CC is a fp conditional flag.
CC = (CC < 16) ? (CC + 16) : CC;
break;
}