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[Sparc] Add support for parsing branches and conditional move instructions with %fcc1-%fcc3 conditional registers.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202616 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju 2014-03-02 06:28:15 +00:00
parent 18fe44cb05
commit a21b315a06
5 changed files with 156 additions and 86 deletions
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17
lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
View File

@ -68,8 +68,7 @@ class SparcAsmParser : public MCTargetAsmParser {
StringRef Name);
OperandMatchResultTy
parseSparcAsmOperand(SparcOperand *&Operand, bool isCall = false,
bool createTokenForFCC = true);
parseSparcAsmOperand(SparcOperand *&Operand, bool isCall = false);
OperandMatchResultTy
parseBranchModifiers(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
@ -633,9 +632,7 @@ parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
SparcOperand *Op = 0;
bool createTokenForFCC = !(Mnemonic == "fcmps" || Mnemonic == "fcmpd"
|| Mnemonic == "fcmpq");
ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"), createTokenForFCC);
ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"));
if (ResTy != MatchOperand_Success || !Op)
return MatchOperand_ParseFail;
@ -646,8 +643,7 @@ parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
}
SparcAsmParser::OperandMatchResultTy
SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op, bool isCall,
bool createTokenForFCC)
SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op, bool isCall)
{
SMLoc S = Parser.getTok().getLoc();
@ -680,13 +676,6 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op, bool isCall,
else
Op = SparcOperand::CreateToken("%icc", S);
break;
case Sparc::FCC0:
if (createTokenForFCC) {
assert(name == "fcc0" && "Cannot handle %fcc other than %fcc0 yet");
Op = SparcOperand::CreateToken("%fcc0", S);
break;
}
}
break;
}

11
lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
View File

@ -146,11 +146,12 @@ void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum,
case SP::BPFCCA:
case SP::BPFCCNT:
case SP::BPFCCANT:
case SP::MOVFCCrr:
case SP::MOVFCCri:
case SP::FMOVS_FCC:
case SP::FMOVD_FCC:
case SP::FMOVQ_FCC: // Make sure CC is a fp conditional flag.
case SP::MOVFCCrr: case SP::V9MOVFCCrr:
case SP::MOVFCCri: case SP::V9MOVFCCri:
case SP::FMOVS_FCC: case SP::V9FMOVS_FCC:
case SP::FMOVD_FCC: case SP::V9FMOVD_FCC:
case SP::FMOVQ_FCC: case SP::V9FMOVQ_FCC:
// Make sure CC is a fp conditional flag.
CC = (CC < 16) ? (CC + 16) : CC;
break;
}

75
lib/Target/Sparc/SparcInstrAliases.td
View File

@ -13,31 +13,52 @@
// Instruction aliases for conditional moves.
// mov<cond> <ccreg> rs2, rd
multiclass cond_mov_alias<string cond, int condVal, string ccreg,
multiclass intcond_mov_alias<string cond, int condVal, string ccreg,
Instruction movrr, Instruction movri,
Instruction fmovs, Instruction fmovd> {
// mov<cond> (%icc|%xcc|%fcc0), rs2, rd
// mov<cond> (%icc|%xcc), rs2, rd
def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
", $rs2, $rd"),
(movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
// mov<cond> (%icc|%xcc|%fcc0), simm11, rd
// mov<cond> (%icc|%xcc), simm11, rd
def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
", $simm11, $rd"),
(movri IntRegs:$rd, i32imm:$simm11, condVal)>;
// fmovs<cond> (%icc|%xcc|%fcc0), $rs2, $rd
// fmovs<cond> (%icc|%xcc), $rs2, $rd
def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg),
", $rs2, $rd"),
(fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
// fmovd<cond> (%icc|%xcc|%fcc0), $rs2, $rd
// fmovd<cond> (%icc|%xcc), $rs2, $rd
def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg),
", $rs2, $rd"),
(fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>;
}
// mov<cond> <ccreg> rs2, rd
multiclass fpcond_mov_alias<string cond, int condVal,
Instruction movrr, Instruction movri,
Instruction fmovs, Instruction fmovd> {
// mov<cond> %fcc[0-3], rs2, rd
def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $rs2, $rd"),
(movrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, condVal)>;
// mov<cond> %fcc[0-3], simm11, rd
def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $simm11, $rd"),
(movri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, condVal)>;
// fmovs<cond> %fcc[0-3], $rs2, $rd
def : InstAlias<!strconcat(!strconcat("fmovs", cond), " $cc, $rs2, $rd"),
(fmovs FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, condVal)>;
// fmovd<cond> %fcc[0-3], $rs2, $rd
def : InstAlias<!strconcat(!strconcat("fmovd", cond), " $cc, $rs2, $rd"),
(fmovd DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, condVal)>;
}
// Instruction aliases for integer conditional branches and moves.
multiclass int_cond_alias<string cond, int condVal> {
@ -99,11 +120,11 @@ multiclass int_cond_alias<string cond, int condVal> {
(BPXCCANT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
defm : cond_mov_alias<cond, condVal, " %icc",
defm : intcond_mov_alias<cond, condVal, " %icc",
MOVICCrr, MOVICCri,
FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>;
defm : cond_mov_alias<cond, condVal, " %xcc",
defm : intcond_mov_alias<cond, condVal, " %xcc",
MOVXCCrr, MOVXCCri,
FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>;
@ -130,36 +151,42 @@ multiclass fp_cond_alias<string cond, int condVal> {
(FBCONDA brtarget:$imm, condVal), 0>;
// fb<cond> %fcc0, $imm
def : InstAlias<!strconcat(!strconcat("fb", cond), " %fcc0, $imm"),
(BPFCC brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
def : InstAlias<!strconcat(!strconcat("fb", cond), " $cc, $imm"),
(BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
Requires<[HasV9]>;
// fb<cond>,pt %fcc0, $imm
def : InstAlias<!strconcat(!strconcat("fb", cond), ",pt %fcc0, $imm"),
(BPFCC brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
def : InstAlias<!strconcat(!strconcat("fb", cond), ",pt $cc, $imm"),
(BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
Requires<[HasV9]>;
// fb<cond>,a %fcc0, $imm
def : InstAlias<!strconcat(!strconcat("fb", cond), ",a %fcc0, $imm"),
(BPFCCA brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $cc, $imm"),
(BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
Requires<[HasV9]>;
// fb<cond>,a,pt %fcc0, $imm
def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pt %fcc0, $imm"),
(BPFCCA brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pt $cc, $imm"),
(BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
Requires<[HasV9]>;
// fb<cond>,pn %fcc0, $imm
def : InstAlias<!strconcat(!strconcat("fb", cond), ",pn %fcc0, $imm"),
(BPFCCNT brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
def : InstAlias<!strconcat(!strconcat("fb", cond), ",pn $cc, $imm"),
(BPFCCNT brtarget:$imm, condVal, FCCRegs:$cc)>,
Requires<[HasV9]>;
// fb<cond>,a,pn %fcc0, $imm
def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pn %fcc0, $imm"),
(BPFCCANT brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pn $cc, $imm"),
(BPFCCANT brtarget:$imm, condVal, FCCRegs:$cc)>, Requires<[HasV9]>;
defm : cond_mov_alias<cond, condVal, " %fcc0",
MOVFCCrr, MOVFCCri,
FMOVS_FCC, FMOVD_FCC>, Requires<[HasV9]>;
defm : fpcond_mov_alias<cond, condVal,
V9MOVFCCrr, V9MOVFCCri,
V9FMOVS_FCC, V9FMOVD_FCC>, Requires<[HasV9]>;
// fmovq<cond> %fcc0, $rs2, $rd
def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %fcc0, $rs2, $rd"),
(FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
def : InstAlias<!strconcat(!strconcat("fmovq", cond), " $cc, $rs2, $rd"),
(V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2,
condVal)>,
Requires<[HasV9, HasHardQuad]>;
}

30
lib/Target/Sparc/SparcInstrInfo.td
View File

@ -1019,7 +1019,7 @@ let Predicates = [HasV9] in {
Requires<[HasHardQuad]>;
}
// Floating-point compare instruction with %fcc0-%fcc1
// Floating-point compare instruction with %fcc0-%fcc3.
def V9FCMPS : F3_3c<2, 0b110101, 0b001010001,
(outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
"fcmps $rd, $rs1, $rs2", []>;
@ -1031,6 +1031,34 @@ def V9FCMPQ : F3_3c<2, 0b110101, 0b001010011,
"fcmpq $rd, $rs1, $rs2", []>,
Requires<[HasHardQuad]>;
// Floating point conditional move instrucitons with %fcc0-%fcc3.
let Predicates = [HasV9] in {
let Constraints = "$f = $rd", intcc = 0 in {
def V9MOVFCCrr
: F4_1<0b101100, (outs IntRegs:$rd),
(ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
"mov$cond $cc, $rs2, $rd", []>;
def V9MOVFCCri
: F4_2<0b101100, (outs IntRegs:$rd),
(ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond),
"mov$cond $cc, $simm11, $rd", []>;
def V9FMOVS_FCC
: F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
(ins FCCRegs:$opf_cc, FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
"fmovs$cond $opf_cc, $rs2, $rd", []>;
def V9FMOVD_FCC
: F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
(ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
"fmovd$cond $opf_cc, $rs2, $rd", []>;
def V9FMOVQ_FCC
: F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
(ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
"fmovq$cond $opf_cc, $rs2, $rd", []>,
Requires<[HasHardQuad]>;
} // Constraints = "$f = $rd", ...
} // let Predicates = [hasV9]
// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
// the top 32-bits before using it. To do this clearing, we use a SRLri X,0.
let rs1 = 0 in

109
test/MC/Sparc/sparc64-ctrl-instructions.s
View File

@ -146,20 +146,20 @@
movo %fcc0, %g1, %g2
! CHECK fmovsne %icc, %f1, %f2 ! encoding: [0x85,0xaa,0x60,0x21]
! CHECK fmovse %icc, %f1, %f2 ! encoding: [0x85,0xa8,0x60,0x21]
! CHECK fmovsg %icc, %f1, %f2 ! encoding: [0x85,0xaa,0xa0,0x21]
! CHECK fmovsle %icc, %f1, %f2 ! encoding: [0x85,0xa8,0xa0,0x21]
! CHECK fmovsge %icc, %f1, %f2 ! encoding: [0x85,0xaa,0xe0,0x21]
! CHECK fmovsl %icc, %f1, %f2 ! encoding: [0x85,0xa8,0xe0,0x21]
! CHECK fmovsgu %icc, %f1, %f2 ! encoding: [0x85,0xab,0x20,0x21]
! CHECK fmovsleu %icc, %f1, %f2 ! encoding: [0x85,0xa9,0x20,0x21]
! CHECK fmovscc %icc, %f1, %f2 ! encoding: [0x85,0xab,0x60,0x21]
! CHECK fmovscs %icc, %f1, %f2 ! encoding: [0x85,0xa9,0x60,0x21]
! CHECK fmovspos %icc, %f1, %f2 ! encoding: [0x85,0xab,0xa0,0x21]
! CHECK fmovsneg %icc, %f1, %f2 ! encoding: [0x85,0xa9,0xa0,0x21]
! CHECK fmovsvc %icc, %f1, %f2 ! encoding: [0x85,0xab,0xe0,0x21]
! CHECK fmovsvs %icc, %f1, %f2 ! encoding: [0x85,0xa9,0xe0,0x21]
! CHECK: fmovsne %icc, %f1, %f2 ! encoding: [0x85,0xaa,0x60,0x21]
! CHECK: fmovse %icc, %f1, %f2 ! encoding: [0x85,0xa8,0x60,0x21]
! CHECK: fmovsg %icc, %f1, %f2 ! encoding: [0x85,0xaa,0xa0,0x21]
! CHECK: fmovsle %icc, %f1, %f2 ! encoding: [0x85,0xa8,0xa0,0x21]
! CHECK: fmovsge %icc, %f1, %f2 ! encoding: [0x85,0xaa,0xe0,0x21]
! CHECK: fmovsl %icc, %f1, %f2 ! encoding: [0x85,0xa8,0xe0,0x21]
! CHECK: fmovsgu %icc, %f1, %f2 ! encoding: [0x85,0xab,0x20,0x21]
! CHECK: fmovsleu %icc, %f1, %f2 ! encoding: [0x85,0xa9,0x20,0x21]
! CHECK: fmovscc %icc, %f1, %f2 ! encoding: [0x85,0xab,0x60,0x21]
! CHECK: fmovscs %icc, %f1, %f2 ! encoding: [0x85,0xa9,0x60,0x21]
! CHECK: fmovspos %icc, %f1, %f2 ! encoding: [0x85,0xab,0xa0,0x21]
! CHECK: fmovsneg %icc, %f1, %f2 ! encoding: [0x85,0xa9,0xa0,0x21]
! CHECK: fmovsvc %icc, %f1, %f2 ! encoding: [0x85,0xab,0xe0,0x21]
! CHECK: fmovsvs %icc, %f1, %f2 ! encoding: [0x85,0xa9,0xe0,0x21]
fmovsne %icc, %f1, %f2
fmovse %icc, %f1, %f2
fmovsg %icc, %f1, %f2
@ -175,20 +175,20 @@
fmovsvc %icc, %f1, %f2
fmovsvs %icc, %f1, %f2
! CHECK fmovsne %xcc, %f1, %f2 ! encoding: [0x85,0xaa,0x70,0x21]
! CHECK fmovse %xcc, %f1, %f2 ! encoding: [0x85,0xa8,0x70,0x21]
! CHECK fmovsg %xcc, %f1, %f2 ! encoding: [0x85,0xaa,0xb0,0x21]
! CHECK fmovsle %xcc, %f1, %f2 ! encoding: [0x85,0xa8,0xb0,0x21]
! CHECK fmovsge %xcc, %f1, %f2 ! encoding: [0x85,0xaa,0xf0,0x21]
! CHECK fmovsl %xcc, %f1, %f2 ! encoding: [0x85,0xa8,0xf0,0x21]
! CHECK fmovsgu %xcc, %f1, %f2 ! encoding: [0x85,0xab,0x30,0x21]
! CHECK fmovsleu %xcc, %f1, %f2 ! encoding: [0x85,0xa9,0x30,0x21]
! CHECK fmovscc %xcc, %f1, %f2 ! encoding: [0x85,0xab,0x70,0x21]
! CHECK fmovscs %xcc, %f1, %f2 ! encoding: [0x85,0xa9,0x70,0x21]
! CHECK fmovspos %xcc, %f1, %f2 ! encoding: [0x85,0xab,0xb0,0x21]
! CHECK fmovsneg %xcc, %f1, %f2 ! encoding: [0x85,0xa9,0xb0,0x21]
! CHECK fmovsvc %xcc, %f1, %f2 ! encoding: [0x85,0xab,0xf0,0x21]
! CHECK fmovsvs %xcc, %f1, %f2 ! encoding: [0x85,0xa9,0xf0,0x21]
! CHECK: fmovsne %xcc, %f1, %f2 ! encoding: [0x85,0xaa,0x70,0x21]
! CHECK: fmovse %xcc, %f1, %f2 ! encoding: [0x85,0xa8,0x70,0x21]
! CHECK: fmovsg %xcc, %f1, %f2 ! encoding: [0x85,0xaa,0xb0,0x21]
! CHECK: fmovsle %xcc, %f1, %f2 ! encoding: [0x85,0xa8,0xb0,0x21]
! CHECK: fmovsge %xcc, %f1, %f2 ! encoding: [0x85,0xaa,0xf0,0x21]
! CHECK: fmovsl %xcc, %f1, %f2 ! encoding: [0x85,0xa8,0xf0,0x21]
! CHECK: fmovsgu %xcc, %f1, %f2 ! encoding: [0x85,0xab,0x30,0x21]
! CHECK: fmovsleu %xcc, %f1, %f2 ! encoding: [0x85,0xa9,0x30,0x21]
! CHECK: fmovscc %xcc, %f1, %f2 ! encoding: [0x85,0xab,0x70,0x21]
! CHECK: fmovscs %xcc, %f1, %f2 ! encoding: [0x85,0xa9,0x70,0x21]
! CHECK: fmovspos %xcc, %f1, %f2 ! encoding: [0x85,0xab,0xb0,0x21]
! CHECK: fmovsneg %xcc, %f1, %f2 ! encoding: [0x85,0xa9,0xb0,0x21]
! CHECK: fmovsvc %xcc, %f1, %f2 ! encoding: [0x85,0xab,0xf0,0x21]
! CHECK: fmovsvs %xcc, %f1, %f2 ! encoding: [0x85,0xa9,0xf0,0x21]
fmovsne %xcc, %f1, %f2
fmovse %xcc, %f1, %f2
fmovsg %xcc, %f1, %f2
@ -204,20 +204,20 @@
fmovsvc %xcc, %f1, %f2
fmovsvs %xcc, %f1, %f2
! CHECK fmovsu %fcc0, %f1, %f2 ! encoding: [0x85,0xa9,0xc0,0x21]
! CHECK fmovsg %fcc0, %f1, %f2 ! encoding: [0x85,0xa9,0x80,0x21]
! CHECK fmovsug %fcc0, %f1, %f2 ! encoding: [0x85,0xa9,0x40,0x21]
! CHECK fmovsl %fcc0, %f1, %f2 ! encoding: [0x85,0xa9,0x00,0x21]
! CHECK fmovsul %fcc0, %f1, %f2 ! encoding: [0x85,0xa8,0xc0,0x21]
! CHECK fmovslg %fcc0, %f1, %f2 ! encoding: [0x85,0xa8,0x80,0x21]
! CHECK fmovsne %fcc0, %f1, %f2 ! encoding: [0x85,0xa8,0x40,0x21]
! CHECK fmovse %fcc0, %f1, %f2 ! encoding: [0x85,0xaa,0x40,0x21]
! CHECK fmovsue %fcc0, %f1, %f2 ! encoding: [0x85,0xaa,0x80,0x21]
! CHECK fmovsge %fcc0, %f1, %f2 ! encoding: [0x85,0xaa,0xc0,0x21]
! CHECK fmovsuge %fcc0, %f1, %f2 ! encoding: [0x85,0xab,0x00,0x21]
! CHECK fmovsle %fcc0, %f1, %f2 ! encoding: [0x85,0xab,0x40,0x21]
! CHECK fmovsule %fcc0, %f1, %f2 ! encoding: [0x85,0xab,0x80,0x21]
! CHECK fmovso %fcc0, %f1, %f2 ! encoding: [0x85,0xab,0xc0,0x21]
! CHECK: fmovsu %fcc0, %f1, %f2 ! encoding: [0x85,0xa9,0xc0,0x21]
! CHECK: fmovsg %fcc0, %f1, %f2 ! encoding: [0x85,0xa9,0x80,0x21]
! CHECK: fmovsug %fcc0, %f1, %f2 ! encoding: [0x85,0xa9,0x40,0x21]
! CHECK: fmovsl %fcc0, %f1, %f2 ! encoding: [0x85,0xa9,0x00,0x21]
! CHECK: fmovsul %fcc0, %f1, %f2 ! encoding: [0x85,0xa8,0xc0,0x21]
! CHECK: fmovslg %fcc0, %f1, %f2 ! encoding: [0x85,0xa8,0x80,0x21]
! CHECK: fmovsne %fcc0, %f1, %f2 ! encoding: [0x85,0xa8,0x40,0x21]
! CHECK: fmovse %fcc0, %f1, %f2 ! encoding: [0x85,0xaa,0x40,0x21]
! CHECK: fmovsue %fcc0, %f1, %f2 ! encoding: [0x85,0xaa,0x80,0x21]
! CHECK: fmovsge %fcc0, %f1, %f2 ! encoding: [0x85,0xaa,0xc0,0x21]
! CHECK: fmovsuge %fcc0, %f1, %f2 ! encoding: [0x85,0xab,0x00,0x21]
! CHECK: fmovsle %fcc0, %f1, %f2 ! encoding: [0x85,0xab,0x40,0x21]
! CHECK: fmovsule %fcc0, %f1, %f2 ! encoding: [0x85,0xab,0x80,0x21]
! CHECK: fmovso %fcc0, %f1, %f2 ! encoding: [0x85,0xab,0xc0,0x21]
fmovsu %fcc0, %f1, %f2
fmovsg %fcc0, %f1, %f2
fmovsug %fcc0, %f1, %f2
@ -1111,3 +1111,28 @@
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
fbo,a,pn %fcc0, .BB0
! CHECK: movu %fcc1, %g1, %g2 ! encoding: [0x85,0x61,0xc8,0x01]
movu %fcc1, %g1, %g2
! CHECK: fmovsg %fcc2, %f1, %f2 ! encoding: [0x85,0xa9,0x90,0x21]
fmovsg %fcc2, %f1, %f2
! CHECK: fbug %fcc3, .BB0 ! encoding: [0x0b,0b01111AAA,A,A]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
fbug %fcc3, .BB0
! CHECK: fbu %fcc3, .BB0 ! encoding: [0x0f,0b01111AAA,A,A]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
fbu,pt %fcc3, .BB0
! CHECK: fbl,a %fcc3, .BB0 ! encoding: [0x29,0b01111AAA,A,A]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
fbl,a %fcc3, .BB0
! CHECK: fbue,pn %fcc3, .BB0 ! encoding: [0x15,0b01110AAA,A,A]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
fbue,pn %fcc3, .BB0
! CHECK: fbne,a,pn %fcc3, .BB0 ! encoding: [0x23,0b01110AAA,A,A]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
fbne,a,pn %fcc3, .BB0