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[ARM] Define subtarget feature "reserve-r9", which is used to decide
whether register r9 should be reserved. This change is needed because we cannot use a backend option to set cl::opt "arm-reserve-r9" when doing LTO. Out-of-tree projects currently using cl::opt option "-arm-reserve-r9" to reserve r9 should make changes to add subtarget feature "reserve-r9" to the IR. rdar://problem/21529937 Differential Revision: http://reviews.llvm.org/D11320 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242737 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -154,6 +154,10 @@ def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",
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"Generate calls via indirect call "
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"Generate calls via indirect call "
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"instructions">;
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"instructions">;
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def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
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"Reserve R9, making it unavailable as "
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"GPR">;
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def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
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def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
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"Don't use movt/movw pairs for 32-bit "
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"Don't use movt/movw pairs for 32-bit "
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"imms">;
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"imms">;
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@ -39,10 +39,6 @@ using namespace llvm;
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#define GET_SUBTARGETINFO_CTOR
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#define GET_SUBTARGETINFO_CTOR
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#include "ARMGenSubtargetInfo.inc"
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#include "ARMGenSubtargetInfo.inc"
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static cl::opt<bool>
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ReserveR9("arm-reserve-r9", cl::Hidden,
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cl::desc("Reserve R9, making it unavailable as GPR"));
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static cl::opt<bool>
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static cl::opt<bool>
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UseFusedMulOps("arm-use-mulops",
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UseFusedMulOps("arm-use-mulops",
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cl::init(true), cl::Hidden);
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cl::init(true), cl::Hidden);
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@ -144,7 +140,7 @@ void ARMSubtarget::initializeEnvironment() {
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UseSoftFloat = false;
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UseSoftFloat = false;
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HasThumb2 = false;
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HasThumb2 = false;
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NoARM = false;
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NoARM = false;
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IsR9Reserved = ReserveR9;
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ReserveR9 = false;
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NoMovt = false;
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NoMovt = false;
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SupportsTailCall = false;
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SupportsTailCall = false;
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HasFP16 = false;
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HasFP16 = false;
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@ -212,13 +208,10 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
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if (isTargetNaCl())
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if (isTargetNaCl())
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stackAlignment = 16;
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stackAlignment = 16;
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if (isTargetMachO()) {
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if (isTargetMachO())
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IsR9Reserved = ReserveR9 || !HasV6Ops;
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SupportsTailCall = !isTargetIOS() || !getTargetTriple().isOSVersionLT(5, 0);
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SupportsTailCall = !isTargetIOS() || !getTargetTriple().isOSVersionLT(5, 0);
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} else {
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else
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IsR9Reserved = ReserveR9;
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SupportsTailCall = !isThumb1Only();
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SupportsTailCall = !isThumb1Only();
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}
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if (Align == DefaultAlign) {
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if (Align == DefaultAlign) {
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// Assume pre-ARMv6 doesn't support unaligned accesses.
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// Assume pre-ARMv6 doesn't support unaligned accesses.
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@ -109,8 +109,8 @@ protected:
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/// NoARM - True if subtarget does not support ARM mode execution.
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/// NoARM - True if subtarget does not support ARM mode execution.
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bool NoARM;
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bool NoARM;
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/// IsR9Reserved - True if R9 is a not available as general purpose register.
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/// ReserveR9 - True if R9 is not available as a general purpose register.
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bool IsR9Reserved;
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bool ReserveR9;
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/// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
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/// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
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/// 32-bit imms (including global addresses).
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/// 32-bit imms (including global addresses).
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@ -413,7 +413,9 @@ public:
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return isThumb1Only() && isMClass();
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return isThumb1Only() && isMClass();
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}
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}
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bool isR9Reserved() const { return IsR9Reserved; }
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bool isR9Reserved() const {
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return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
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}
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bool useMovt(const MachineFunction &MF) const;
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bool useMovt(const MachineFunction &MF) const;
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@ -2,7 +2,7 @@
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; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic \
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; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic \
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; RUN: -mattr=+v6 | grep r9
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; RUN: -mattr=+v6 | grep r9
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; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic \
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; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic \
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; RUN: -mattr=+v6 -arm-reserve-r9 -ifcvt-limit=0 -stats 2>&1 | grep asm-printer
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; RUN: -mattr=+v6,+reserve-r9 -ifcvt-limit=0 -stats 2>&1 | grep asm-printer
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; | grep 35
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; | grep 35
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define void @test(i32 %tmp56222, i32 %tmp36224, i32 %tmp46223, i32 %i.0196.0.ph, i32 %tmp8, i32* %tmp1011, i32** %tmp1, i32* %d2.1.out, i32* %d3.1.out, i32* %d0.1.out, i32* %d1.1.out) {
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define void @test(i32 %tmp56222, i32 %tmp36224, i32 %tmp46223, i32 %i.0196.0.ph, i32 %tmp8, i32* %tmp1011, i32** %tmp1, i32* %d2.1.out, i32* %d3.1.out, i32* %d0.1.out, i32* %d1.1.out) {
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@ -122,7 +122,7 @@
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; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -relocation-model=dynamic-no-pic | FileCheck %s --check-prefix=RELOC-OTHER
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; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -relocation-model=dynamic-no-pic | FileCheck %s --check-prefix=RELOC-OTHER
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; RUN: llc < %s -mtriple=arm-none-linux-gnueabi | FileCheck %s --check-prefix=RELOC-OTHER
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; RUN: llc < %s -mtriple=arm-none-linux-gnueabi | FileCheck %s --check-prefix=RELOC-OTHER
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; RUN: llc < %s -mtriple=arm-none-linux-gnueabi | FileCheck %s --check-prefix=PCS-R9-USE
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; RUN: llc < %s -mtriple=arm-none-linux-gnueabi | FileCheck %s --check-prefix=PCS-R9-USE
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; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -arm-reserve-r9 | FileCheck %s --check-prefix=PCS-R9-RESERVE
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; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+reserve-r9 | FileCheck %s --check-prefix=PCS-R9-RESERVE
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; ARMv8.1a (AArch32)
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; ARMv8.1a (AArch32)
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; RUN: llc < %s -mtriple=armv8.1a-none-linux-gnueabi -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN
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; RUN: llc < %s -mtriple=armv8.1a-none-linux-gnueabi -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN
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