From a249914462c7b8f0c25b21eca77df264455290ee Mon Sep 17 00:00:00 2001
From: Chad Rosier <mcrosier@codeaurora.org>
Date: Wed, 16 Oct 2013 21:04:34 +0000
Subject: [PATCH] [AArch64] Add support for NEON scalar absolute value
 instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192842 91177308-0d34-0410-b5e6-96231b3b80d8
---
 include/llvm/IR/IntrinsicsAArch64.td          |  4 +++
 lib/Target/AArch64/AArch64InstrNEON.td        | 29 ++++++++++++++-----
 test/CodeGen/AArch64/neon-scalar-abs.ll       | 12 ++++++++
 test/MC/AArch64/neon-diagnostics.s            | 10 +++++++
 test/MC/AArch64/neon-scalar-abs.s             |  8 +++++
 .../AArch64/neon-instructions.txt             |  6 ++++
 6 files changed, 61 insertions(+), 8 deletions(-)

diff --git a/include/llvm/IR/IntrinsicsAArch64.td b/include/llvm/IR/IntrinsicsAArch64.td
index 79bd9695897..d11c672ef99 100644
--- a/include/llvm/IR/IntrinsicsAArch64.td
+++ b/include/llvm/IR/IntrinsicsAArch64.td
@@ -196,4 +196,8 @@ def int_aarch64_neon_vuqadd : Neon_2Arg_Intrinsic;
 
 // Scalar Unsigned Saturating Accumulated of Signed Value
 def int_aarch64_neon_vsqadd : Neon_2Arg_Intrinsic;
+
+// Scalar Absolute Value
+def int_aarch64_neon_vabs :
+  Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty], [IntrNoMem]>;
 }
diff --git a/lib/Target/AArch64/AArch64InstrNEON.td b/lib/Target/AArch64/AArch64InstrNEON.td
index 12f8fb093f0..96a5482f99e 100644
--- a/lib/Target/AArch64/AArch64InstrNEON.td
+++ b/lib/Target/AArch64/AArch64InstrNEON.td
@@ -3245,7 +3245,15 @@ multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode,
                           [], NoItinerary>;
 }
 
-multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>{
+multiclass NeonI_Scalar2SameMisc_D_size<bit u, bits<5> opcode, string asmop> {
+  def dd: NeonI_Scalar2SameMisc<u, 0b11, opcode,
+                         (outs FPR64:$Rd), (ins FPR64:$Rn),
+                         !strconcat(asmop, " $Rd, $Rn"),
+                         [], NoItinerary>;
+}
+
+multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>
+  : NeonI_Scalar2SameMisc_D_size<u, opcode, asmop> {
   def bb : NeonI_Scalar2SameMisc<u, 0b00, opcode,
                           (outs FPR8:$Rd), (ins FPR8:$Rn),
                           !strconcat(asmop, " $Rd, $Rn"),
@@ -3258,10 +3266,6 @@ multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>{
                           (outs FPR32:$Rd), (ins FPR32:$Rn),
                           !strconcat(asmop, " $Rd, $Rn"),
                           [], NoItinerary>;
-  def dd: NeonI_Scalar2SameMisc<u, 0b11, opcode,
-                         (outs FPR64:$Rd), (ins FPR64:$Rn),
-                         !strconcat(asmop, " $Rd, $Rn"),
-                         [], NoItinerary>;
 }
 
 multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode,
@@ -3318,19 +3322,24 @@ class Neon_Scalar2SameMisc_cmpz_D_size_patterns<SDPatternOperator opnode,
   : Pat<(v1i64 (opnode (v1i64 VPR64:$Rn), (v1i64 (bitconvert (v8i8 Neon_immAllZeros))))),
         (INSTD VPR64:$Rn, 0)>;
 
+multiclass Neon_Scalar2SameMisc_D_size_patterns<SDPatternOperator opnode,
+                                                Instruction INSTD> {
+  def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn))),
+            (INSTD FPR64:$Rn)>;
+}
+
 multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode,
                                                    Instruction INSTB,
                                                    Instruction INSTH,
                                                    Instruction INSTS,
-                                                   Instruction INSTD> {
+                                                   Instruction INSTD>
+  : Neon_Scalar2SameMisc_D_size_patterns<opnode, INSTD> {
   def : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn))),
             (INSTB FPR8:$Rn)>;
   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn))),
             (INSTH FPR16:$Rn)>;
   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn))),
             (INSTS FPR32:$Rn)>;
-  def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn))),
-            (INSTD FPR64:$Rn)>;
 }
 
 multiclass Neon_Scalar2SameMisc_accum_BHSD_size_patterns<
@@ -3567,6 +3576,10 @@ def CMLTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01010, "cmlt">;
 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcltz,
                                                 CMLTddi>;
 
+// Scalar Absolute Value
+defm ABS : NeonI_Scalar2SameMisc_D_size<0b0, 0b01011, "abs">;
+defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vabs, ABSdd>;
+
 // Scalar Signed Saturating Absolute Value
 defm SQABS : NeonI_Scalar2SameMisc_BHSD_size<0b0, 0b00111, "sqabs">;
 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqabs,
diff --git a/test/CodeGen/AArch64/neon-scalar-abs.ll b/test/CodeGen/AArch64/neon-scalar-abs.ll
index 7a1c73a4e8d..03a89e043e5 100644
--- a/test/CodeGen/AArch64/neon-scalar-abs.ll
+++ b/test/CodeGen/AArch64/neon-scalar-abs.ll
@@ -1,5 +1,17 @@
 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
 
+define i64 @test_vabsd_s64(i64 %a) {
+; CHECK: test_vabsd_s64
+; CHECK: abs {{d[0-9]+}}, {{d[0-9]+}}
+entry:
+  %vabs.i = insertelement <1 x i64> undef, i64 %a, i32 0
+  %vabs1.i = tail call <1 x i64> @llvm.aarch64.neon.vabs(<1 x i64> %vabs.i)
+  %0 = extractelement <1 x i64> %vabs1.i, i32 0
+  ret i64 %0
+}
+
+declare <1 x i64> @llvm.aarch64.neon.vabs(<1 x i64>)
+
 define i8 @test_vqabsb_s8(i8 %a) {
 ; CHECK: test_vqabsb_s8
 ; CHECK: sqabs {{b[0-9]+}}, {{b[0-9]+}}
diff --git a/test/MC/AArch64/neon-diagnostics.s b/test/MC/AArch64/neon-diagnostics.s
index 0a688178cf9..ddd80ea1787 100644
--- a/test/MC/AArch64/neon-diagnostics.s
+++ b/test/MC/AArch64/neon-diagnostics.s
@@ -4440,3 +4440,13 @@
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        usqadd d0, b1
 // CHECK-ERROR:                   ^
+
+//----------------------------------------------------------------------
+// Scalar Absolute Value
+//----------------------------------------------------------------------
+
+    abs d29, s24
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        abs d29, s24
+// CHECK-ERROR:                 ^
diff --git a/test/MC/AArch64/neon-scalar-abs.s b/test/MC/AArch64/neon-scalar-abs.s
index 5e10752350e..ddcaa9dfefc 100644
--- a/test/MC/AArch64/neon-scalar-abs.s
+++ b/test/MC/AArch64/neon-scalar-abs.s
@@ -4,6 +4,14 @@
 
 //----------------------------------------------------------------------
 // Scalar Absolute Value
+//----------------------------------------------------------------------
+
+    abs d29, d24
+
+// CHECK: abs d29, d24    // encoding: [0x1d,0xbb,0xe0,0x5e]
+
+//----------------------------------------------------------------------
+// Scalar Signed Saturating Absolute Value
 //----------------------------------------------------------------------
 
     sqabs b19, b14
diff --git a/test/MC/Disassembler/AArch64/neon-instructions.txt b/test/MC/Disassembler/AArch64/neon-instructions.txt
index 4d28da55453..81fffd6c7cb 100644
--- a/test/MC/Disassembler/AArch64/neon-instructions.txt
+++ b/test/MC/Disassembler/AArch64/neon-instructions.txt
@@ -1603,6 +1603,12 @@
 #----------------------------------------------------------------------
 # Scalar Absolute Value
 #----------------------------------------------------------------------
+# CHECK: abs d29, d24
+0x1d,0xbb,0xe0,0x5e
+
+#----------------------------------------------------------------------
+# Scalar Signed Saturating Absolute Value
+#----------------------------------------------------------------------
 # CHECK: sqabs b19, b14
 # CHECK: sqabs h21, h15
 # CHECK: sqabs s20, s12