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Fit long lines into 80 cols via creative space elimination

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16353 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2004-09-15 01:40:18 +00:00
parent 3559a93f5e
commit a2700194ae
1 changed files with 4 additions and 4 deletions
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8
lib/Target/X86/X86RegisterInfo.td
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@ -36,10 +36,10 @@ let Namespace = "X86" in {
def SI : RegisterGroup<"SI", [ESI]>; def DI : RegisterGroup<"DI", [EDI]>;
// 8-bit registers
def AL : RegisterGroup<"AL", [AX, EAX]>; def CL : RegisterGroup<"CL", [CX, ECX]>;
def DL : RegisterGroup<"DL", [DX, EDX]>; def BL : RegisterGroup<"BL", [BX, EBX]>;
def AH : RegisterGroup<"AH", [AX, EAX]>; def CH : RegisterGroup<"CH", [CX, ECX]>;
def DH : RegisterGroup<"DH", [DX, EDX]>; def BH : RegisterGroup<"BH", [BX, EBX]>;
def AL : RegisterGroup<"AL", [AX,EAX]>; def CL : RegisterGroup<"CL",[CX,ECX]>;
def DL : RegisterGroup<"DL", [DX,EDX]>; def BL : RegisterGroup<"BL",[BX,EBX]>;
def AH : RegisterGroup<"AH", [AX,EAX]>; def CH : RegisterGroup<"CH",[CX,ECX]>;
def DH : RegisterGroup<"DH", [DX,EDX]>; def BH : RegisterGroup<"BH",[BX,EBX]>;
// Pseudo Floating Point registers
def FP0 : Register<"FP0">; def FP1 : Register<"FP1">;