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R600/SI: Select V_BFE_U32 for and+shift with a non-literal offset

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233079 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Marek Olsak 2015-03-24 13:40:34 +00:00
parent 226f794fba
commit a2705bbd42
5 changed files with 24 additions and 17 deletions
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22
lib/Target/R600/AMDGPUInstructions.td
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@ -578,22 +578,20 @@ class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
// Bitfield extract patterns
/*
def IMMZeroBasedBitfieldMask : PatLeaf <(imm), [{
return isMask_32(N->getZExtValue());
}]>;
XXX: The BFE pattern is not working correctly because the XForm is not being
applied.
def IMMPopCount : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(countPopulation(N->getZExtValue()),
MVT::i32);
}]>;
def legalshift32 : ImmLeaf <i32, [{return Imm >=0 && Imm < 32;}]>;
def bfemask : PatLeaf <(imm), [{return isMask_32(N->getZExtValue());}],
SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(countTrailingOnes(N->getZExtValue()), MVT::i32);}]>>;
class BFEPattern <Instruction BFE> : Pat <
(and (srl i32:$x, legalshift32:$y), bfemask:$z),
(BFE $x, $y, $z)
class BFEPattern <Instruction BFE, Instruction MOV> : Pat <
(i32 (and (i32 (srl i32:$src, i32:$rshift)), IMMZeroBasedBitfieldMask:$mask)),
(BFE $src, $rshift, (MOV (i32 (IMMPopCount $mask))))
>;
*/
// rotr pattern
class ROTRPattern <Instruction BIT_ALIGN> : Pat <
(rotr i32:$src0, i32:$src1),

5
lib/Target/R600/EvergreenInstructions.td
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@ -287,9 +287,8 @@ def BFE_INT_eg : R600_3OP <0x5, "BFE_INT",
VecALU
>;
// XXX: This pattern is broken, disabling for now. See comment in
// AMDGPUInstructions.td for more info.
// def : BFEPattern <BFE_UINT_eg>;
def : BFEPattern <BFE_UINT_eg, MOV_IMM_I32>;
def BFI_INT_eg : R600_3OP <0x06, "BFI_INT",
[(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))],
VecALU

2
lib/Target/R600/SIInstructions.td
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@ -3339,6 +3339,8 @@ multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> {
defm : BFMPatterns <i32, S_BFM_B32, S_MOV_B32>;
// FIXME: defm : BFMPatterns <i64, S_BFM_B64, S_MOV_B64>;
def : BFEPattern <V_BFE_U32, S_MOV_B32>;
//===----------------------------------------------------------------------===//
// Fract Patterns
//===----------------------------------------------------------------------===//

2
test/CodeGen/R600/bfe_uint.ll
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@ -1,7 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; XFAIL: *
; CHECK: {{^}}bfe_def:
; CHECK: BFE_UINT
define void @bfe_def(i32 addrspace(1)* %out, i32 %x) {

10
test/CodeGen/R600/llvm.AMDGPU.bfe.u32.ll
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@ -586,6 +586,16 @@ define void @lshr_and(i32 addrspace(1)* %out, i32 %a) nounwind {
ret void
}
; FUNC-LABEL: {{^}}v_lshr_and:
; SI: v_bfe_u32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}, 3
; SI: buffer_store_dword
define void @v_lshr_and(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%c = lshr i32 %a, %b
%d = and i32 %c, 7
store i32 %d, i32 addrspace(1)* %out, align 8
ret void
}
; FUNC-LABEL: {{^}}and_lshr:
; SI: s_bfe_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0x30006
; SI: buffer_store_dword