6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-03-28 21:38:44 +00:00
Code Issues Projects Releases Wiki Activity

Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149142 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Devang Patel 2012-01-27 19:48:28 +00:00
parent a21bb20f59
commit a28101e61a
2 changed files with 7 additions and 3 deletions
lib/Target/X86/AsmParser
X86AsmParser.cpp
test/MC/X86
intel-syntax.s

8
lib/Target/X86/AsmParser/X86AsmParser.cpp

@ -610,7 +610,6 @@ X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg,
// Parse BaseReg
if (ParseRegister(BaseReg, Start, End)) {
// Handle '[' 'symbol' ']'
const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
if (getParser().ParseExpression(Disp, End)) return 0;
if (getLexer().isNot(AsmToken::RBrac))
return ErrorOperand(Start, "Expected ']' token!");
@ -624,8 +623,11 @@ X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg,
if (getLexer().is(AsmToken::RBrac)) {
// Handle '[' number ']'
Parser.Lex();
return X86Operand::CreateMem(MCConstantExpr::Create(Val, getContext()),
Start, End, Size);
const MCExpr *Disp = MCConstantExpr::Create(Val, getContext());
if (SegReg)
return X86Operand::CreateMem(SegReg, Disp, 0, 0, Scale,
Start, End, Size);
return X86Operand::CreateMem(Disp, Start, End, Size);
} else if (getLexer().is(AsmToken::Star)) {
// Handle '[' Scale*IndexReg ']'
Parser.Lex();

2
test/MC/X86/intel-syntax.s

@ -61,4 +61,6 @@ _main:
lea R8D, DWORD PTR [4*RDI]
// CHECK: movl _fnan(,%ecx,4), %ecx
mov ECX, DWORD PTR [4*ECX + _fnan]
// CHECK: movq %fs:320, %rax
mov RAX, QWORD PTR FS:[320]
ret