Silence anonymous type in anonymous union warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177135 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/ExecutionEngine/GenericValue.h

@@ -24,11 +24,15 @@ typedef void* PointerTy;
 class APInt;
 
 struct GenericValue {
+  struct IntPair {
+    unsigned int first;
+    unsigned int second;
+  };
   union {
     double          DoubleVal;
     float           FloatVal;
     PointerTy       PointerVal;
-    struct { unsigned int first; unsigned int second; } UIntPairVal;
+    struct IntPair  UIntPairVal;
     unsigned char   Untyped[8];
   };
   APInt IntVal;   // also used for long doubles

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

@@ -160,44 +160,53 @@ private:
 
   SMLoc StartLoc, EndLoc;
 
-  union {
-    struct {
+  struct ImmWithLSLOp {
     const MCExpr *Val;
     unsigned ShiftAmount;
     bool ImplicitAmount;
-    } ImmWithLSL;
+  };
 
-    struct {
+  struct CondCodeOp {
     A64CC::CondCodes Code;
-    } CondCode;
+  };
 
-    struct {
+  struct FPImmOp {
     double Val;
-    } FPImm;
+  };
 
-    struct {
+  struct ImmOp {
     const MCExpr *Val;
-    } Imm;
+  };
 
-    struct {
+  struct RegOp {
     unsigned RegNum;
-    } Reg;
+  };
 
-    struct {
+  struct ShiftExtendOp {
     A64SE::ShiftExtSpecifiers ShiftType;
     unsigned Amount;
     bool ImplicitAmount;
-    } ShiftExtend;
+  };
 
-    struct {
+  struct SysRegOp {
     const char *Data;
     unsigned Length;
-    } SysReg;
+  };
 
-    struct {
+  struct TokOp {
     const char *Data;
     unsigned Length;
-    } Tok;
+  };
+
+  union {
+    struct ImmWithLSLOp ImmWithLSL;
+    struct CondCodeOp CondCode;
+    struct FPImmOp FPImm;
+    struct ImmOp Imm;
+    struct RegOp Reg;
+    struct ShiftExtendOp ShiftExtend;
+    struct SysRegOp SysReg;
+    struct TokOp Tok;
   };
 
   AArch64Operand(KindTy K, SMLoc S, SMLoc E)

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

@@ -316,62 +316,61 @@ class ARMOperand : public MCParsedAsmOperand {
   SMLoc StartLoc, EndLoc;
   SmallVector<unsigned, 8> Registers;
 
-  union {
-    struct {
+  struct CCOp {
     ARMCC::CondCodes Val;
-    } CC;
+  };
 
-    struct {
+  struct CopOp {
     unsigned Val;
-    } Cop;
+  };
 
-    struct {
+  struct CoprocOptionOp {
     unsigned Val;
-    } CoprocOption;
+  };
 
-    struct {
+  struct ITMaskOp {
     unsigned Mask:4;
-    } ITMask;
+  };
 
-    struct {
+  struct MBOptOp {
     ARM_MB::MemBOpt Val;
-    } MBOpt;
+  };
 
-    struct {
+  struct IFlagsOp {
     ARM_PROC::IFlags Val;
-    } IFlags;
+  };
 
-    struct {
+  struct MMaskOp {
     unsigned Val;
-    } MMask;
+  };
 
-    struct {
+  struct TokOp {
     const char *Data;
     unsigned Length;
-    } Tok;
+  };
 
-    struct {
+  struct RegOp {
     unsigned RegNum;
-    } Reg;
+  };
 
   // A vector register list is a sequential list of 1 to 4 registers.
-    struct {
+  struct VectorListOp {
     unsigned RegNum;
     unsigned Count;
     unsigned LaneIndex;
     bool isDoubleSpaced;
-    } VectorList;
+  };
 
-    struct {
+  struct VectorIndexOp {
     unsigned Val;
-    } VectorIndex;
+  };
 
-    struct {
+  struct ImmOp {
     const MCExpr *Val;
-    } Imm;
+  };
 
   /// Combined record for all forms of ARM address expressions.
-    struct {
+  struct MemoryOp {
     unsigned BaseRegNum;
     // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
     // was specified.
@@ -382,37 +381,62 @@ class ARMOperand : public MCParsedAsmOperand {
     unsigned Alignment;       // 0 = no alignment specified
     // n = alignment in bytes (2, 4, 8, 16, or 32)
     unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
-    } Memory;
+  };
 
-    struct {
+  struct PostIdxRegOp {
     unsigned RegNum;
     bool isAdd;
     ARM_AM::ShiftOpc ShiftTy;
     unsigned ShiftImm;
-    } PostIdxReg;
+  };
 
-    struct {
+  struct ShifterImmOp {
     bool isASR;
     unsigned Imm;
-    } ShifterImm;
-    struct {
+  };
+
+  struct RegShiftedRegOp {
     ARM_AM::ShiftOpc ShiftTy;
     unsigned SrcReg;
     unsigned ShiftReg;
     unsigned ShiftImm;
-    } RegShiftedReg;
-    struct {
+  };
+
+  struct RegShiftedImmOp {
     ARM_AM::ShiftOpc ShiftTy;
     unsigned SrcReg;
     unsigned ShiftImm;
-    } RegShiftedImm;
-    struct {
+  };
+
+  struct RotImmOp {
     unsigned Imm;
-    } RotImm;
-    struct {
+  };
+
+  struct BitfieldOp {
     unsigned LSB;
     unsigned Width;
-    } Bitfield;
+  };
+
+  union {
+    struct CCOp CC;
+    struct CopOp Cop;
+    struct CoprocOptionOp CoprocOption;
+    struct MBOptOp MBOpt;
+    struct ITMaskOp ITMask;
+    struct IFlagsOp IFlags;
+    struct MMaskOp MMask;
+    struct TokOp Tok;
+    struct RegOp Reg;
+    struct VectorListOp VectorList;
+    struct VectorIndexOp VectorIndex;
+    struct ImmOp Imm;
+    struct MemoryOp Memory;
+    struct PostIdxRegOp PostIdxReg;
+    struct ShifterImmOp ShifterImm;
+    struct RegShiftedRegOp RegShiftedReg;
+    struct RegShiftedImmOp RegShiftedImm;
+    struct RotImmOp RotImm;
+    struct BitfieldOp Bitfield;
   };
 
   ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}

lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp

@@ -82,29 +82,35 @@ struct MBlazeOperand : public MCParsedAsmOperand {
 
   SMLoc StartLoc, EndLoc;
 
-  union {
-    struct {
+  struct TokOp {
     const char *Data;
     unsigned Length;
-    } Tok;
+  };
 
-    struct {
+  struct RegOp {
     unsigned RegNum;
-    } Reg;
+  };
 
-    struct {
+  struct ImmOp {
     const MCExpr *Val;
-    } Imm;
+  };
 
-    struct {
+  struct MemOp {
     unsigned Base;
     unsigned OffReg;
     const MCExpr *Off;
-    } Mem;
+  };
 
-    struct {
+  struct FslImmOp {
     const MCExpr *Val;
-    } FslImm;
+  };
+
+  union {
+    struct TokOp Tok;
+    struct RegOp Reg;
+    struct ImmOp Imm;
+    struct MemOp Mem;
+    struct FslImmOp FslImm;
   };
 
   MBlazeOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

@@ -211,25 +211,30 @@ private:
 
   MipsOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
 
-  union {
-    struct {
+  struct Token {
     const char *Data;
     unsigned Length;
-    } Tok;
+  };
 
-    struct {
+  struct RegOp {
     unsigned RegNum;
     RegisterKind Kind;
-    } Reg;
+  };
 
-    struct {
+  struct ImmOp {
     const MCExpr *Val;
-    } Imm;
+  };
 
-    struct {
+  struct MemOp {
     unsigned Base;
     const MCExpr *Off;
-    } Mem;
+  };
+
+  union {
+    struct Token Tok;
+    struct RegOp Reg;
+    struct ImmOp Imm;
+    struct MemOp Mem;
   };
 
   SMLoc StartLoc, EndLoc;

lib/Target/X86/AsmParser/X86AsmParser.cpp

@@ -170,22 +170,21 @@ struct X86Operand : public MCParsedAsmOperand {
   SMLoc OffsetOfLoc;
   bool AddressOf;
 
-  union {
-    struct {
+  struct TokOp {
     const char *Data;
     unsigned Length;
-    } Tok;
+  };
 
-    struct {
+  struct RegOp {
     unsigned RegNo;
-    } Reg;
+  };
 
-    struct {
+  struct ImmOp {
     const MCExpr *Val;
     bool NeedAsmRewrite;
-    } Imm;
+  };
 
-    struct {
+  struct MemOp {
     unsigned SegReg;
     const MCExpr *Disp;
     unsigned BaseReg;
@@ -193,7 +192,13 @@ struct X86Operand : public MCParsedAsmOperand {
     unsigned Scale;
     unsigned Size;
     bool NeedSizeDir;
-    } Mem;
+  };
+
+  union {
+    struct TokOp Tok;
+    struct RegOp Reg;
+    struct ImmOp Imm;
+    struct MemOp Mem;
   };
 
   X86Operand(KindTy K, SMLoc Start, SMLoc End)