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expand PICLDR MC lowering to handle other PICLDR and PICSTR versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114183 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1351,10 +1351,17 @@ void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
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OutStreamer.EmitInstruction(AddInst);
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return;
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}
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case ARM::PICLDR: {
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case ARM::PICSTR:
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case ARM::PICSTRB:
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case ARM::PICSTRH:
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case ARM::PICLDR:
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case ARM::PICLDRB:
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case ARM::PICLDRH:
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case ARM::PICLDRSB:
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case ARM::PICLDRSH: {
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// This is a pseudo op for a label + instruction sequence, which looks like:
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// LPC0:
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// ldr r0, [pc, r0]
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// OP r0, [pc, r0]
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// The LCP0 label is referenced by a constant pool entry in order to get
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// a PC-relative address at the ldr instruction.
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@ -1367,16 +1374,29 @@ void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
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OutStreamer.EmitLabel(Label);
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// Form and emit the load
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MCInst LdrInst;
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LdrInst.setOpcode(ARM::LDR);
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LdrInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
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LdrInst.addOperand(MCOperand::CreateReg(ARM::PC));
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LdrInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
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LdrInst.addOperand(MCOperand::CreateImm(0));
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unsigned Opcode;
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switch (MI->getOpcode()) {
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default:
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llvm_unreachable("Unexpected opcode!");
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case ARM::PICSTR: Opcode = ARM::STR; break;
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case ARM::PICSTRB: Opcode = ARM::STRB; break;
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case ARM::PICSTRH: Opcode = ARM::STRH; break;
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case ARM::PICLDR: Opcode = ARM::LDR; break;
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case ARM::PICLDRB: Opcode = ARM::LDRB; break;
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case ARM::PICLDRH: Opcode = ARM::LDRH; break;
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case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
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case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
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}
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MCInst LdStInst;
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LdStInst.setOpcode(Opcode);
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LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
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LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
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LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
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LdStInst.addOperand(MCOperand::CreateImm(0));
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// Add predicate operands.
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LdrInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
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LdrInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
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OutStreamer.EmitInstruction(LdrInst);
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LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
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LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
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OutStreamer.EmitInstruction(LdStInst);
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return;
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}
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