6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-20 14:29:27 +00:00
Code Issues Projects Releases Wiki Activity

Generate SETX for 64-bit integers!

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1007 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve 2001-10-28 21:41:46 +00:00
parent c7b2e5c81e
commit a2a7094662
1 changed files with 28 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
lib/Target/SparcV9/SparcV9InstrInfo.cpp
View File

@ -24,21 +24,35 @@
static inline MachineInstr* static inline MachineInstr*
CreateIntSetInstruction(int64_t C, bool isSigned, Value* dest) CreateIntSetInstruction(int64_t C, bool isSigned, Value* dest,
vector<TmpInstruction*>& tempVec)
{ {
MachineInstr* minstr; MachineInstr* minstr;
uint64_t absC = (C >= 0)? C : -C;
if (absC > (unsigned int) ~0)
{ // C does not fit in 32 bits
TmpInstruction* tmpReg =
new TmpInstruction(Instruction::UserOp1, NULL, NULL);
tempVec.push_back(tmpReg);
minstr = new MachineInstr(SETX);
minstr->SetMachineOperand(0, MachineOperand::MO_SignExtendedImmed, C);
minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, tmpReg,
/*isdef*/ true);
minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,dest);
}
if (isSigned) if (isSigned)
{ {
minstr = new MachineInstr(SETSW); minstr = new MachineInstr(SETSW);
minstr->SetMachineOperand(0, MachineOperand::MO_SignExtendedImmed, C); minstr->SetMachineOperand(0, MachineOperand::MO_SignExtendedImmed, C);
minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, dest);
} }
else else
{ {
minstr = new MachineInstr(SETUW); minstr = new MachineInstr(SETUW);
minstr->SetMachineOperand(0, MachineOperand::MO_UnextendedImmed, C); minstr->SetMachineOperand(0, MachineOperand::MO_UnextendedImmed, C);
}
minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, dest); minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, dest);
}
return minstr; return minstr;
} }
@ -92,20 +106,24 @@ UltraSparcInstrInfo::CreateCodeToLoadConst(Value* val,
bool isValidConstant; bool isValidConstant;
int64_t C = GetConstantValueAsSignedInt(val, isValidConstant); int64_t C = GetConstantValueAsSignedInt(val, isValidConstant);
assert(isValidConstant && "Unrecognized constant"); assert(isValidConstant && "Unrecognized constant");
minstr = CreateIntSetInstruction(C, valType->isSigned(), dest); minstr = CreateIntSetInstruction(C, valType->isSigned(), dest, tempVec);
minstrVec.push_back(minstr); minstrVec.push_back(minstr);
} }
else else
{ {
// Make an instruction sequence to load the constant, viz: // Make an instruction sequence to load the constant, viz:
// SETSW <addr-of-constant>, addrReg // SETX <addr-of-constant>, tmpReg, addrReg
// LOAD /*addr*/ addrReg, /*offset*/ 0, dest // LOAD /*addr*/ addrReg, /*offset*/ 0, dest
// Only the SETSW is needed if `val' is a GlobalValue, i.e,. it is // Only the SETX is needed if `val' is a GlobalValue, i.e,. it is
// itself a constant address. Otherwise, both are needed. // itself a constant address. Otherwise, both are needed.
Value* addrVal; Value* addrVal;
int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0 int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
TmpInstruction* tmpReg =
new TmpInstruction(Instruction::UserOp1, val, NULL);
tempVec.push_back(tmpReg);
if (isa<ConstPoolVal>(val)) if (isa<ConstPoolVal>(val))
{ {
// Create another TmpInstruction for the hidden integer register // Create another TmpInstruction for the hidden integer register
@ -117,9 +135,11 @@ UltraSparcInstrInfo::CreateCodeToLoadConst(Value* val,
else else
addrVal = dest; addrVal = dest;
minstr = new MachineInstr(SETUW); minstr = new MachineInstr(SETX);
minstr->SetMachineOperand(0, MachineOperand::MO_PCRelativeDisp, val); minstr->SetMachineOperand(0, MachineOperand::MO_PCRelativeDisp, val);
minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,addrVal); minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, tmpReg,
/*isdef*/ true);
minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,addrVal);
minstrVec.push_back(minstr); minstrVec.push_back(minstr);
if (isa<ConstPoolVal>(val)) if (isa<ConstPoolVal>(val))