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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
Improve an integer select optimization in two ways:
1. generalize
(select (x == 0), -1, 0) -> (sign_bit (x - 1))
to:
(select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
2. Handle the identical pattern that happens with !=:
(select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
cmov is often high latency and can't fold immediates or
memory operands. For example for (x == 0) ? -1 : 1, before
we got:
< testb %sil, %sil
< movl $-1, %ecx
< movl $1, %eax
< cmovel %ecx, %eax
now we get:
> cmpb $1, %sil
> sbbl %eax, %eax
> orl $1, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120929 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
bced6a1b8f
commit
a2b5600e61
@ -7208,10 +7208,17 @@ static bool isX86LogicalCmp(SDValue Op) {
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return false;
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}
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static bool isZero(SDValue V) {
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ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
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return C && C->isNullValue();
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}
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SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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bool addTest = true;
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SDValue Cond = Op.getOperand(0);
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DebugLoc dl = Op.getDebugLoc();
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SDValue Op1 = Op.getOperand(1);
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SDValue Op2 = Op.getOperand(2);
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DebugLoc DL = Op.getDebugLoc();
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SDValue CC;
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if (Cond.getOpcode() == ISD::SETCC) {
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@ -7220,30 +7227,35 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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Cond = NewCond;
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}
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// (select (x == 0), -1, 0) -> (sign_bit (x - 1))
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SDValue Op1 = Op.getOperand(1);
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SDValue Op2 = Op.getOperand(2);
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// (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
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// (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
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if (Cond.getOpcode() == X86ISD::SETCC &&
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cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
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Cond.getOperand(1).getOpcode() == X86ISD::CMP) {
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SDValue Cmp = Cond.getOperand(1);
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if (Cmp.getOpcode() == X86ISD::CMP) {
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
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unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
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if ((N1C && N1C->isAllOnesValue() && CondCode == X86::COND_E) ||
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(N2C && N2C->isAllOnesValue() && CondCode == X86::COND_NE)) {
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SDValue Y = CondCode == X86::COND_NE ? Op1 : Op2;
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SDValue CmpOp0 = Cmp.getOperand(0);
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Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
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CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
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SDValue Res =
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DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
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DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
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ConstantSDNode *RHSC =
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dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
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if (N1C && N1C->isAllOnesValue() &&
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N2C && N2C->isNullValue() &&
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RHSC && RHSC->isNullValue()) {
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SDValue CmpOp0 = Cmp.getOperand(0);
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Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
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CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
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return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
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DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
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}
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if (N2C == 0 || !N2C->isNullValue())
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Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
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return Res;
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}
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}
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// Look pass (and (setcc_carry (cmp ...)), 1).
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// Look past (and (setcc_carry (cmp ...)), 1).
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if (Cond.getOpcode() == ISD::AND &&
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Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
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ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
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@ -7281,7 +7293,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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// We know the result of AND is compared against zero. Try to match
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// it to BT.
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if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
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SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
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SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
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if (NewSetCC.getNode()) {
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CC = NewSetCC.getOperand(0);
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Cond = NewSetCC.getOperand(1);
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@ -7299,7 +7311,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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// condition is true.
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SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
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SDValue Ops[] = { Op2, Op1, CC, Cond };
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return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
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return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
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}
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// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
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@ -86,6 +86,7 @@ define x86_fp80 @test7(i32 %tmp8) nounwind {
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%tmp9 = icmp sgt i32 %tmp8, -1 ; <i1> [#uses=1]
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%retval = select i1 %tmp9, x86_fp80 0xK4005B400000000000000, x86_fp80 0xK40078700000000000000
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ret x86_fp80 %retval
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; CHECK: test7:
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; CHECK: leaq
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; CHECK: fldt (%r{{.}}x,%r{{.}}x)
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}
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@ -96,4 +97,61 @@ define void @test8(i1 %c, <6 x i32>* %dst.addr, <6 x i32> %src1,<6 x i32> %src2)
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%val = sub <6 x i32> %x, < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
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store <6 x i32> %val, <6 x i32>* %dst.addr
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ret void
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; CHECK: test8:
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}
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;; Test integer select between values and constants.
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define i64 @test9(i64 %x, i64 %y) nounwind readnone ssp noredzone {
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%cmp = icmp ne i64 %x, 0
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%cond = select i1 %cmp, i64 %y, i64 -1
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ret i64 %cond
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; CHECK: test9:
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; CHECK: cmpq $1, %rdi
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; CHECK: sbbq %rax, %rax
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; CHECK: orq %rsi, %rax
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; CHECK: ret
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}
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;; Same as test9
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define i64 @test9a(i64 %x, i64 %y) nounwind readnone ssp noredzone {
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%cmp = icmp eq i64 %x, 0
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%cond = select i1 %cmp, i64 -1, i64 %y
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ret i64 %cond
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; CHECK: test9a:
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; CHECK: cmpq $1, %rdi
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; CHECK: sbbq %rax, %rax
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; CHECK: orq %rsi, %rax
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; CHECK: ret
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}
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define i64 @test9b(i64 %x, i64 %y) nounwind readnone ssp noredzone {
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%cmp = icmp eq i64 %x, 0
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%A = sext i1 %cmp to i64
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%cond = or i64 %y, %A
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ret i64 %cond
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; CHECK: test9b:
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; CHECK: cmpq $1, %rdi
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; CHECK: sbbq %rax, %rax
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; CHECK: orq %rsi, %rax
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; CHECK: ret
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}
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;; Select between -1 and 1.
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define i64 @test10(i64 %x, i64 %y) nounwind readnone ssp noredzone {
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%cmp = icmp eq i64 %x, 0
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%cond = select i1 %cmp, i64 -1, i64 1
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ret i64 %cond
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; CHECK: test10:
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; CHECK: cmpq $1, %rdi
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; CHECK: sbbq %rax, %rax
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; CHECK: orq $1, %rax
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; CHECK: ret
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}
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