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Fix UMULO support for 2x register width to allow the full
range without a libcall to a new mulo<mode> libcall that we'd have to create. Finishes the rest of rdar://9090077 and rdar://9210061 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133318 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2160,6 +2160,27 @@ void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
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const Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
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DebugLoc dl = N->getDebugLoc();
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// A divide for UMULO should be faster than a function call.
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if (N->getOpcode() == ISD::UMULO) {
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SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
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DebugLoc DL = N->getDebugLoc();
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SDValue MUL = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS);
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SplitInteger(MUL, Lo, Hi);
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// A divide for UMULO will be faster than a function call. Select to
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// make sure we aren't using 0.
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SDValue isZero = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
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RHS, DAG.getConstant(0, VT), ISD::SETNE);
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SDValue NotZero = DAG.getNode(ISD::SELECT, dl, VT, isZero,
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DAG.getConstant(1, VT), RHS);
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SDValue DIV = DAG.getNode(ISD::UDIV, DL, LHS.getValueType(), MUL, NotZero);
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SDValue Overflow;
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Overflow = DAG.getSetCC(DL, N->getValueType(1), DIV, LHS, ISD::SETNE);
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ReplaceValueWith(SDValue(N, 1), Overflow);
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return;
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}
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// Replace this with a libcall that will check overflow.
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RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
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if (VT == MVT::i32)
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@ -2,9 +2,8 @@
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%0 = type { i64, i64 }
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%1 = type { i128, i1 }
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@.str = private unnamed_addr constant [11 x i8] c"%llx %llx\0A\00", align 1
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define %0 @x(i64 %a.coerce0, i64 %a.coerce1, i64 %b.coerce0, i64 %b.coerce1) nounwind uwtable ssp {
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; CHECK: x
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entry:
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%tmp16 = zext i64 %a.coerce0 to i128
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%tmp11 = zext i64 %a.coerce1 to i128
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@ -33,6 +32,50 @@ nooverflow: ; preds = %entry
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ret %0 %tmp24
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}
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define %0 @foo(i64 %a.coerce0, i64 %a.coerce1, i64 %b.coerce0, i64 %b.coerce1) nounwind uwtable ssp {
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entry:
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; CHECK: foo
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%retval = alloca i128, align 16
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%coerce = alloca i128, align 16
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%a.addr = alloca i128, align 16
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%coerce1 = alloca i128, align 16
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%b.addr = alloca i128, align 16
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%0 = bitcast i128* %coerce to %0*
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%1 = getelementptr %0* %0, i32 0, i32 0
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store i64 %a.coerce0, i64* %1
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%2 = getelementptr %0* %0, i32 0, i32 1
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store i64 %a.coerce1, i64* %2
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%a = load i128* %coerce, align 16
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store i128 %a, i128* %a.addr, align 16
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%3 = bitcast i128* %coerce1 to %0*
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%4 = getelementptr %0* %3, i32 0, i32 0
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store i64 %b.coerce0, i64* %4
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%5 = getelementptr %0* %3, i32 0, i32 1
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store i64 %b.coerce1, i64* %5
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%b = load i128* %coerce1, align 16
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store i128 %b, i128* %b.addr, align 16
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%tmp = load i128* %a.addr, align 16
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%tmp2 = load i128* %b.addr, align 16
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%6 = call %1 @llvm.umul.with.overflow.i128(i128 %tmp, i128 %tmp2)
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; CHECK: cmov
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; CHECK: divti3
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%7 = extractvalue %1 %6, 0
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%8 = extractvalue %1 %6, 1
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br i1 %8, label %overflow, label %nooverflow
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overflow: ; preds = %entry
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call void @llvm.trap()
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unreachable
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nooverflow: ; preds = %entry
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store i128 %7, i128* %retval
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%9 = bitcast i128* %retval to %0*
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%10 = load %0* %9, align 1
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ret %0 %10
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}
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declare %1 @llvm.umul.with.overflow.i128(i128, i128) nounwind readnone
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declare %1 @llvm.smul.with.overflow.i128(i128, i128) nounwind readnone
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declare void @llvm.trap() nounwind
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