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https://github.com/c64scene-ar/llvm-6502.git
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[Hexagon] Implement commoning of GetElementPtr instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241714 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek
parent
c783eb28f7
commit
a307401165
@ -16,6 +16,7 @@ add_llvm_target(HexagonCodeGen
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HexagonAsmPrinter.cpp
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HexagonBitTracker.cpp
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HexagonCFGOptimizer.cpp
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HexagonCommonGEP.cpp
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HexagonCopyToCombine.cpp
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HexagonExpandCondsets.cpp
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HexagonExpandPredSpillCode.cpp
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1325
lib/Target/Hexagon/HexagonCommonGEP.cpp
Normal file
1325
lib/Target/Hexagon/HexagonCommonGEP.cpp
Normal file
File diff suppressed because it is too large
Load Diff
@ -40,6 +40,10 @@ static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
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static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
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cl::Hidden, cl::desc("Generate \"insert\" instructions"));
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static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
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cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
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/// HexagonTargetMachineModule - Note that this is used on hosts that
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/// cannot link in a library unless there are references into the
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/// library. In particular, it seems that it is not possible to get
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@ -62,6 +66,7 @@ SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
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createVLIWMachineSched);
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namespace llvm {
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FunctionPass *createHexagonCommonGEP();
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FunctionPass *createHexagonExpandCondsets();
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FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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@ -124,6 +129,7 @@ public:
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return createVLIWMachineSched(C);
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}
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void addIRPasses() override;
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bool addInstSelector() override;
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void addPreRegAlloc() override;
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void addPostRegAlloc() override;
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@ -136,6 +142,14 @@ TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new HexagonPassConfig(this, PM);
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}
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void HexagonPassConfig::addIRPasses() {
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TargetPassConfig::addIRPasses();
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bool NoOpt = (getOptLevel() == CodeGenOpt::None);
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if (!NoOpt && EnableCommGEP)
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addPass(createHexagonCommonGEP());
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}
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bool HexagonPassConfig::addInstSelector() {
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HexagonTargetMachine &TM = getHexagonTargetMachine();
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bool NoOpt = (getOptLevel() == CodeGenOpt::None);
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37
test/CodeGen/Hexagon/common-gep-basic.ll
Normal file
37
test/CodeGen/Hexagon/common-gep-basic.ll
Normal file
@ -0,0 +1,37 @@
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; RUN: llc -O2 -march=hexagon < %s | FileCheck %s
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; CHECK: mpyi
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; CHECK-NOT: mpyi
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; The mpyis from the two GEPs should be commoned out.
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target datalayout = "e-m:e-p:32:32-i64:64-a:0-v32:32-n16:32"
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target triple = "hexagon-unknown--elf"
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%struct.s_t = type { %struct.anon, i32 }
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%struct.anon = type { i32, [5 x i32] }
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@g = common global [100 x %struct.s_t] zeroinitializer, align 8
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; Function Attrs: nounwind
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define void @foo(i32 %x) #0 {
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entry:
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%cmp = icmp slt i32 %x, 90
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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%arrayidx1 = getelementptr inbounds [100 x %struct.s_t], [100 x %struct.s_t]* @g, i32 0, i32 %x, i32 0, i32 1, i32 2
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tail call void @bar(i32* %arrayidx1) #0
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br label %if.end
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if.else: ; preds = %entry
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%arrayidx5 = getelementptr inbounds [100 x %struct.s_t], [100 x %struct.s_t]* @g, i32 0, i32 %x, i32 0, i32 1, i32 3
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tail call void @bar(i32* %arrayidx5) #0
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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ret void
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}
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declare void @bar(i32*) #0
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attributes #0 = { nounwind }
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76
test/CodeGen/Hexagon/common-gep-icm.ll
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76
test/CodeGen/Hexagon/common-gep-icm.ll
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@ -0,0 +1,76 @@
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; RUN: llc -O2 -march=hexagon < %s | FileCheck %s
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; Rely on the comments generated by llc. Make sure there are no add/addasl
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; instructions in while.body13 (before the loads).
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; CHECK: while.body13
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; CHECK-NOT: add
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; CHECK: memw
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%struct.1 = type { i32, i32 }
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%struct.2 = type { [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [3 x i32], [24 x i32], [8 x %struct.1], [5 x i32] }
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@A1 = global i64 zeroinitializer
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@A2 = global i64 zeroinitializer
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@B1 = global i32 zeroinitializer
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@B2 = global i32 zeroinitializer
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@C1 = global i8 zeroinitializer
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declare i32 @llvm.hexagon.S2.cl0(i32) nounwind readnone
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declare i32 @llvm.hexagon.S2.setbit.r(i32, i32) nounwind readnone
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declare i64 @llvm.hexagon.M2.vmpy2s.s0(i32, i32) nounwind readnone
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declare i64 @llvm.hexagon.M2.vmac2s.s0(i64, i32, i32) nounwind readnone
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declare i64 @llvm.hexagon.A2.vaddws(i64, i64) nounwind readnone
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declare i64 @llvm.hexagon.A2.vsubws(i64, i64) nounwind readnone
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declare i32 @llvm.hexagon.A4.modwrapu(i32, i32) nounwind readnone
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define void @foo(i32 %n) nounwind {
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entry:
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br label %while.body
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while.body:
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%count = phi i32 [ 0, %entry ], [ %next, %while.end ]
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%idx = phi i32 [ 0, %entry ], [ %15, %while.end ]
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%0 = load i32, i32* @B1, align 4
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%1 = load i32, i32* @B2, align 8
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%2 = and i32 %1, %0
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br label %while.body13
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while.body13: ; preds = %while.body, %if.end
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%3 = phi i64 [ %13, %if.end ], [ 0, %while.body ]
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%4 = phi i64 [ %14, %if.end ], [ 0, %while.body ]
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%m = phi i32 [ %6, %if.end ], [ %2, %while.body ]
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%5 = tail call i32 @llvm.hexagon.S2.cl0(i32 %m)
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%6 = tail call i32 @llvm.hexagon.S2.setbit.r(i32 %m, i32 %5)
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%cgep85 = getelementptr [10 x %struct.2], [10 x %struct.2]* inttoptr (i32 -121502345 to [10 x %struct.2]*), i32 0, i32 %idx
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%cgep90 = getelementptr %struct.2, %struct.2* %cgep85, i32 0, i32 12, i32 %5
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%7 = load i32, i32* %cgep90, align 4
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%8 = tail call i64 @llvm.hexagon.M2.vmpy2s.s0(i32 %7, i32 %7)
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%cgep91 = getelementptr %struct.2, %struct.2* %cgep85, i32 0, i32 13, i32 %5
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%9 = load i32, i32* %cgep91, align 4
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%10 = tail call i64 @llvm.hexagon.M2.vmac2s.s0(i64 %8, i32 %9, i32 %9)
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%11 = load i8, i8* @C1, align 1
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%and24 = and i8 %11, 1
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%cmp = icmp eq i8 %and24, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %while.body13
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%12 = tail call i64 @llvm.hexagon.A2.vaddws(i64 %3, i64 %10)
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store i64 %12, i64* @A1, align 8
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br label %if.end
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if.end: ; preds = %if.then, %while.body13
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%13 = phi i64 [ %12, %if.then ], [ %3, %while.body13 ]
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%14 = tail call i64 @llvm.hexagon.A2.vsubws(i64 %4, i64 %10)
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%tobool12 = icmp eq i32 %6, 0
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br i1 %tobool12, label %while.end, label %while.body13
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while.end:
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%add40 = add i32 %idx, 1
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%15 = tail call i32 @llvm.hexagon.A4.modwrapu(i32 %add40, i32 10) nounwind
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%next = add i32 %count, 1
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%cc = icmp eq i32 %next, %n
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br i1 %cc, label %end, label %while.body
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end:
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store i64 %10, i64* @A2, align 8
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ret void
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}
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