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Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139522 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2011-09-12 18:56:30 +00:00
parent 29da5e6855
commit a3157b4026
3 changed files with 545 additions and 0 deletions
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32
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -301,6 +301,9 @@ static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
#include "ARMGenDisassemblerTables.inc"
#include "ARMGenInstrInfo.inc"
@ -2755,6 +2758,35 @@ static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
return S;
}
static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success;
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned addr = fieldFromInstruction32(Insn, 0, 8);
addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
addr |= Rn << 9;
unsigned load = fieldFromInstruction32(Insn, 20, 1);
if (!load) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail;
if (load) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
}
if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
return MCDisassembler::Fail;
return S;
}
static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {