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Add LOAD/STORE support for MMX.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34978 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2007-03-06 18:53:42 +00:00
parent 7a9a0695f2
commit a31bd27f12
2 changed files with 46 additions and 21 deletions
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3
lib/Target/X86/X86ISelLowering.cpp
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@ -327,6 +327,9 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
// FIXME: add MMX packed arithmetics // FIXME: add MMX packed arithmetics
setOperationAction(ISD::LOAD, MVT::v8i8, Legal);
setOperationAction(ISD::LOAD, MVT::v4i16, Legal);
setOperationAction(ISD::LOAD, MVT::v2i32, Legal);
setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);

64
lib/Target/X86/X86InstrMMX.td
View File

@ -13,7 +13,10 @@
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Instruction templates // Instruction templates
//===----------------------------------------------------------------------===//
// MMXI - MMX instructions with TB prefix. // MMXI - MMX instructions with TB prefix.
// MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes. // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix. // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
@ -30,33 +33,42 @@ def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst),
[(set VR64:$dst, (v8i8 (undef)))]>, [(set VR64:$dst, (v8i8 (undef)))]>,
Requires<[HasMMX]>; Requires<[HasMMX]>;
def : Pat<(v8i8 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>;
def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>; def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>;
def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>; def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>;
// EMMS //===----------------------------------------------------------------------===//
def EMMS : I<0x77, RawFrm, (ops), "emms", [(int_x86_mmx_emms)]>, TB, // MMX Pattern Fragments
Requires<[HasMMX]>; //===----------------------------------------------------------------------===//
def loadv2i32 : PatFrag<(ops node:$ptr), (v2i32 (load node:$ptr))>;
//===----------------------------------------------------------------------===//
// MMX EMMS Instruction
//===----------------------------------------------------------------------===//
def EMMS : MMXI<0x77, RawFrm, (ops), "emms", [(int_x86_mmx_emms)]>;
//===----------------------------------------------------------------------===//
// MMX Scalar Instructions
//===----------------------------------------------------------------------===//
// Move Instructions // Move Instructions
def MOVD64rr : I<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src), def MOVD64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
"movd {$src, $dst|$dst, $src}", []>, TB, "movd {$src, $dst|$dst, $src}", []>;
Requires<[HasMMX]>; def MOVD64rm : MMXI<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
def MOVD64rm : I<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src), "movd {$src, $dst|$dst, $src}", []>;
"movd {$src, $dst|$dst, $src}", []>, TB, def MOVD64mr : MMXI<0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src),
Requires<[HasMMX]>; "movd {$src, $dst|$dst, $src}", []>;
def MOVD64mr : I<0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src),
"movd {$src, $dst|$dst, $src}", []>, TB,
Requires<[HasMMX]>;
def MOVQ64rr : I<0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src), def MOVQ64rr : MMXI<0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src),
"movq {$src, $dst|$dst, $src}", []>, TB, "movq {$src, $dst|$dst, $src}", []>;
Requires<[HasMMX]>; def MOVQ64rm : MMXI<0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src),
def MOVQ64rm : I<0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src), "movq {$src, $dst|$dst, $src}",
"movq {$src, $dst|$dst, $src}", []>, TB, [(set VR64:$dst, (loadv2i32 addr:$src))]>;
Requires<[HasMMX]>; def MOVQ64mr : MMXI<0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
def MOVQ64mr : I<0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src), "movq {$src, $dst|$dst, $src}",
"movq {$src, $dst|$dst, $src}", []>, TB, [(store (v2i32 VR64:$src), addr:$dst)]>;
Requires<[HasMMX]>;
// Conversion instructions // Conversion instructions
def CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src), def CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
@ -98,3 +110,13 @@ def MOVNTQ : I<0xE7, MRMDestMem, (ops i64mem:$dst, VR64:$src),
def MASKMOVQ : I<0xF7, MRMDestMem, (ops VR64:$src, VR64:$mask), def MASKMOVQ : I<0xF7, MRMDestMem, (ops VR64:$src, VR64:$mask),
"maskmovq {$mask, $src|$src, $mask}", []>, TB, "maskmovq {$mask, $src|$src, $mask}", []>, TB,
Requires<[HasMMX]>; Requires<[HasMMX]>;
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
//===----------------------------------------------------------------------===//
// Store 64-bit integer vector values.
def : Pat<(store (v8i8 VR64:$src), addr:$dst),
(MOVQ64mr addr:$dst, VR64:$src)>;
def : Pat<(store (v4i16 VR64:$src), addr:$dst),
(MOVQ64mr addr:$dst, VR64:$src)>;