6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-25 13:24:46 +00:00
Code Issues Projects Releases Wiki Activity

Add support to tablegen for specifying subregister classes on a per register class basis.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37572 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Christopher Lamb
2007-06-13 22:20:15 +00:00
parent 13e8b51e3e
commit a321125e8b
5 changed files with 98 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
utils/TableGen/CodeGenRegisters.h
View File

@@ -38,6 +38,7 @@ namespace llvm {
std::vector<MVT::ValueType> VTs;
unsigned SpillSize;
unsigned SpillAlignment;
std::vector<Record*> SubRegClasses;
std::string MethodProtos, MethodBodies;
const std::string &getName() const;

10
utils/TableGen/CodeGenTarget.cpp
View File

@@ -199,6 +199,16 @@ CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
Elements.push_back(Reg);
}
std::vector<Record*> SubRegClassList =
R->getValueAsListOfDefs("SubRegClassList");
for (unsigned i = 0, e = SubRegClassList.size(); i != e; ++i) {
Record *SubRegClass = SubRegClassList[i];
if (!SubRegClass->isSubClassOf("RegisterClass"))
throw "Register Class member '" + SubRegClass->getName() +
"' does not derive from the RegisterClass class!";
SubRegClasses.push_back(SubRegClass);
}
// Allow targets to override the size in bits of the RegisterClass.
unsigned Size = R->getValueAsInt("Size");

39
utils/TableGen/RegisterInfoEmitter.cpp
View File

@@ -224,6 +224,44 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
std::map<unsigned, std::set<unsigned> > SuperClassMap;
OS << "\n";
// Emit the sub-register classes for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc];
// Give the register class a legal C name if it's anonymous.
std::string Name = RC.TheDef->getName();
OS << " // " << Name
<< " Sub-register Classess...\n"
<< " static const TargetRegisterClass* const "
<< Name << "SubRegClasses [] = {\n ";
bool Empty = true;
for (unsigned subrc = 0, e2 = RC.SubRegClasses.size();
subrc != e2; ++subrc) {
unsigned rc2 = 0, e2 = RegisterClasses.size();
for (; rc2 != e2; ++rc2) {
const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
if (RC.SubRegClasses[subrc]->getName() == RC2.getName()) {
if (!Empty) OS << ", ";
OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
Empty = false;
break;
}
}
if (rc2 == e2)
throw "Register Class member '" +
RC.SubRegClasses[subrc]->getName() +
"' is not a valid RegisterClass!";
}
OS << (!Empty ? ", " : "") << "NULL";
OS << "\n };\n\n";
}
// Emit the sub-classes array for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc];
@@ -304,6 +342,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
<< RC.getName() + "VTs" << ", "
<< RC.getName() + "Subclasses" << ", "
<< RC.getName() + "Superclasses" << ", "
<< RC.getName() + "SubRegClasses" << ", "
<< RC.SpillSize/8 << ", "
<< RC.SpillAlignment/8 << ", " << RC.getName() << ", "
<< RC.getName() << " + " << RC.Elements.size() << ") {}\n";