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Add support to tablegen for specifying subregister classes on a per register class basis.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37572 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Christopher Lamb
2007-06-13 22:20:15 +00:00
parent 13e8b51e3e
commit a321125e8b
5 changed files with 98 additions and 0 deletions
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utils/TableGen/CodeGenTarget.cpp
+10
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@@ -199,6 +199,16 @@ CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
Elements.push_back(Reg);
}
std::vector<Record*> SubRegClassList =
R->getValueAsListOfDefs("SubRegClassList");
for (unsigned i = 0, e = SubRegClassList.size(); i != e; ++i) {
Record *SubRegClass = SubRegClassList[i];
if (!SubRegClass->isSubClassOf("RegisterClass"))
throw "Register Class member '" + SubRegClass->getName() +
"' does not derive from the RegisterClass class!";
SubRegClasses.push_back(SubRegClass);
}
// Allow targets to override the size in bits of the RegisterClass.
unsigned Size = R->getValueAsInt("Size");