From a3231ba237b1a5113a71253eab50c6b7a5239132 Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Thu, 9 Aug 2007 22:25:35 +0000
Subject: [PATCH] Temporarily backing out this change until we know why some
 dejagnu tests are failing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40973 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/X86RegisterInfo.td | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td
index a5b218999c4..c40dcb93550 100644
--- a/lib/Target/X86/X86RegisterInfo.td
+++ b/lib/Target/X86/X86RegisterInfo.td
@@ -419,12 +419,11 @@ def GR64 : RegisterClass<"X86", [i64], 64,
 
 // GR16, GR32 subclasses which contain registers that have GR8 sub-registers.
 // These should only be used for 32-bit mode.
-def GR8_ : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL, AH, CH, DH, BH]>;
 def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
-  let SubRegClassList = [GR8_];
+  let SubRegClassList = [GR8];
 }
 def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
-  let SubRegClassList = [GR8_, GR16_];
+  let SubRegClassList = [GR8, GR16];
 }
 
 // Scalar SSE2 floating point registers.