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R600/SI: Don't select SI-only VOP3 opcodes on VI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226186 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1656,9 +1656,6 @@ defm V_ALIGNBYTE_B32 : VOP3Inst <vop3<0x14f, 0x1cf>, "v_alignbyte_b32",
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VOP_I32_I32_I32_I32
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>;
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// Only on SI
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defm V_MULLIT_F32 : VOP3Inst <vop3<0x150>, "v_mullit_f32",
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VOP_F32_F32_F32_F32>;
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defm V_MIN3_F32 : VOP3Inst <vop3<0x151>, "v_min3_f32",
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VOP_F32_F32_F32_F32, AMDGPUfmin3>;
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@ -1699,20 +1696,6 @@ defm V_DIV_FIXUP_F64 : VOP3Inst <
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} // let SchedRW = [WriteDouble]
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defm V_LSHL_B64 : VOP3Inst <vop3<0x161>, "v_lshl_b64",
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VOP_I64_I64_I32, shl
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>;
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// Only on SI
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defm V_LSHR_B64 : VOP3Inst <vop3<0x162>, "v_lshr_b64",
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VOP_I64_I64_I32, srl
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>;
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// Only on SI
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defm V_ASHR_I64 : VOP3Inst <vop3<0x163>, "v_ashr_i64",
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VOP_I64_I64_I32, sra
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>;
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let SchedRW = [WriteDouble] in {
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let isCommutable = 1 in {
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@ -1785,6 +1768,26 @@ defm V_TRIG_PREOP_F64 : VOP3Inst <
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} // let SchedRW = [WriteDouble]
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// These instructions only exist on SI and CI
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let SubtargetPredicate = isSICI in {
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defm V_LSHL_B64 : VOP3Inst <vop3<0x161>, "v_lshl_b64",
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VOP_I64_I64_I32, shl
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>;
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defm V_LSHR_B64 : VOP3Inst <vop3<0x162>, "v_lshr_b64",
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VOP_I64_I64_I32, srl
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>;
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defm V_ASHR_I64 : VOP3Inst <vop3<0x163>, "v_ashr_i64",
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VOP_I64_I64_I32, sra
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>;
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defm V_MULLIT_F32 : VOP3Inst <vop3<0x150>, "v_mullit_f32",
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VOP_F32_F32_F32_F32>;
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} // End SubtargetPredicate = isSICI
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//===----------------------------------------------------------------------===//
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// Pseudo Instructions
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//===----------------------------------------------------------------------===//
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