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GR16_ sub-register class should be GR8_, not GR8. That is, it should only be 8-bit registers in 32-bit mode. Ditto for GR32_.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40970 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-08-09 18:05:17 +00:00
parent ab081c7195
commit a333b41af9
1 changed files with 4 additions and 3 deletions
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7
lib/Target/X86/X86RegisterInfo.td
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@ -417,13 +417,14 @@ def GR64 : RegisterClass<"X86", [i64], 64,
} }
// GR16, GR32 subclasses which contain registers that have R8 sub-registers. // GR16, GR32 subclasses which contain registers that have GR8 sub-registers.
// These should only be used for 32-bit mode. // These should only be used for 32-bit mode.
def GR8_ : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL, AH, CH, DH, BH]>;
def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> { def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
let SubRegClassList = [GR8]; let SubRegClassList = [GR8_];
} }
def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> { def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
let SubRegClassList = [GR8, GR16]; let SubRegClassList = [GR8_, GR16_];
} }
// Scalar SSE2 floating point registers. // Scalar SSE2 floating point registers.