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https://github.com/c64scene-ar/llvm-6502.git
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Clean up predicates on ARM target instruction aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138249 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
b113ec55e8
commit
a33b31be45
@ -218,10 +218,21 @@ def shr_imm64 : Operand<i32> {
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let DecoderMethod = "DecodeShiftRight64Imm";
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}
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//===----------------------------------------------------------------------===//
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// ARM Assembler alias templates.
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//
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class ARMInstAlias<string Asm, dag Result, bit Emit = 0b1>
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: InstAlias<Asm, Result, Emit>, Requires<[IsARM]>;
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class tInstAlias<string Asm, dag Result, bit Emit = 0b1>
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: InstAlias<Asm, Result, Emit>, Requires<[IsThumb]>;
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class t2InstAlias<string Asm, dag Result, bit Emit = 0b1>
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: InstAlias<Asm, Result, Emit>, Requires<[IsThumb2]>;
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//===----------------------------------------------------------------------===//
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// ARM Instruction templates.
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//
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class InstTemplate<AddrMode am, int sz, IndexMode im,
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Format f, Domain d, string cstr, InstrItinClass itin>
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: Instruction {
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@ -4751,75 +4751,71 @@ def : MnemonicAlias<"stmea", "stm">;
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// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
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// shift amount is zero (i.e., unspecified).
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def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
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(PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
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(PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>,
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Requires<[IsARM, HasV6]>;
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def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
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(PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
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(PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>,
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Requires<[IsARM, HasV6]>;
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// PUSH/POP aliases for STM/LDM
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def : InstAlias<"push${p} $regs",
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(STMDB_UPD SP, pred:$p, reglist:$regs)>;
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def : InstAlias<"pop${p} $regs",
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(LDMIA_UPD SP, pred:$p, reglist:$regs)>;
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def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
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def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
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// RSB two-operand forms (optional explicit destination operand)
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def : InstAlias<"rsb${s}${p} $Rdn, $imm",
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(RSBri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>,
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Requires<[IsARM]>;
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def : InstAlias<"rsb${s}${p} $Rdn, $Rm",
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(RSBrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>,
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Requires<[IsARM]>;
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def : InstAlias<"rsb${s}${p} $Rdn, $shift",
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def : ARMInstAlias<"rsb${s}${p} $Rdn, $imm",
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(RSBri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>;
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def : ARMInstAlias<"rsb${s}${p} $Rdn, $Rm",
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(RSBrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>;
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def : ARMInstAlias<"rsb${s}${p} $Rdn, $shift",
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(RSBrsi GPR:$Rdn, GPR:$Rdn, so_reg_imm:$shift, pred:$p,
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cc_out:$s)>, Requires<[IsARM]>;
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def : InstAlias<"rsb${s}${p} $Rdn, $shift",
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cc_out:$s)>;
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def : ARMInstAlias<"rsb${s}${p} $Rdn, $shift",
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(RSBrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p,
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cc_out:$s)>, Requires<[IsARM]>;
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cc_out:$s)>;
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// RSC two-operand forms (optional explicit destination operand)
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def : InstAlias<"rsc${s}${p} $Rdn, $imm",
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(RSCri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>,
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Requires<[IsARM]>;
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def : InstAlias<"rsc${s}${p} $Rdn, $Rm",
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(RSCrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>,
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Requires<[IsARM]>;
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def : InstAlias<"rsc${s}${p} $Rdn, $shift",
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def : ARMInstAlias<"rsc${s}${p} $Rdn, $imm",
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(RSCri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>;
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def : ARMInstAlias<"rsc${s}${p} $Rdn, $Rm",
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(RSCrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>;
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def : ARMInstAlias<"rsc${s}${p} $Rdn, $shift",
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(RSCrsi GPR:$Rdn, GPR:$Rdn, so_reg_imm:$shift, pred:$p,
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cc_out:$s)>, Requires<[IsARM]>;
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def : InstAlias<"rsc${s}${p} $Rdn, $shift",
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cc_out:$s)>;
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def : ARMInstAlias<"rsc${s}${p} $Rdn, $shift",
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(RSCrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p,
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cc_out:$s)>, Requires<[IsARM]>;
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cc_out:$s)>;
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// SSAT/USAT optional shift operand.
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def : InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
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def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
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(SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
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def : InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
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def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
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(USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
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// Extend instruction optional rotate operand.
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def : InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
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def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
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(SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
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def : InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
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def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
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(SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
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def : InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
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def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
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(SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
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def : InstAlias<"sxtb${p} $Rd, $Rm",
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def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
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(SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
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def : InstAlias<"sxtb16${p} $Rd, $Rm",
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def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
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(SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
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def : InstAlias<"sxth${p} $Rd, $Rm",
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def : ARMInstAlias<"sxth${p} $Rd, $Rm",
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(SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
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def : InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
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def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
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(UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
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def : InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
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def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
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(UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
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def : InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
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def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
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(UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
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def : InstAlias<"uxtb${p} $Rd, $Rm",
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def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
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(UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
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def : InstAlias<"uxtb16${p} $Rd, $Rm",
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def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
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(UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
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def : InstAlias<"uxth${p} $Rd, $Rm",
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def : ARMInstAlias<"uxth${p} $Rd, $Rm",
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(UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
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@ -1017,9 +1017,8 @@ def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
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}
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// Because we have an explicit tMOVSr below, we need an alias to handle
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// the immediate "movs" form here. Blech.
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def : InstAlias <"movs $Rdn, $imm",
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(tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>,
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Requires<[IsThumb]>;
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def : tInstAlias <"movs $Rdn, $imm",
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(tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>;
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// A7-73: MOV(2) - mov setting flag.
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@ -1061,9 +1060,8 @@ def tMUL : // A8.6.105 T1
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let AsmMatchConverter = "cvtThumbMultiply";
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}
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def : InstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
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pred:$p)>,
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Requires<[IsThumb]>;
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def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
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pred:$p)>;
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// Move inverse register
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def tMVN : // A8.6.107
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@ -1115,9 +1113,8 @@ def tRSB : // A8.6.141
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"rsb", "\t$Rd, $Rn, #0",
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[(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
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def : InstAlias<"neg${s}${p} $Rd, $Rm",
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(tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>,
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Requires<[IsThumb]>;
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def : tInstAlias<"neg${s}${p} $Rd, $Rm",
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(tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;
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// Subtract with carry register
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let Uses = [CPSR] in
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@ -504,21 +504,18 @@ multiclass T2I_bin_irs<bits<4> opcod, string opc,
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}
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// Assembly aliases for optional destination operand when it's the same
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// as the source operand.
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def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
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def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
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(!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
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t2_so_imm:$imm, pred:$p,
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cc_out:$s)>,
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Requires<[IsThumb2]>;
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def : InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
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cc_out:$s)>;
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def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
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(!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
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rGPR:$Rm, pred:$p,
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cc_out:$s)>,
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Requires<[IsThumb2]>;
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def : InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
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cc_out:$s)>;
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def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
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(!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
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t2_so_reg:$shift, pred:$p,
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cc_out:$s)>,
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Requires<[IsThumb2]>;
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cc_out:$s)>;
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}
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/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
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@ -1557,9 +1554,8 @@ def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
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let Inst{15} = 0;
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}
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def : InstAlias<"mov${s}${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
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pred:$p, cc_out:$s)>,
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Requires<[IsThumb2]>;
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def : t2InstAlias<"mov${s}${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
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pred:$p, cc_out:$s)>;
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let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
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def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
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