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Starting to refactor Target to separate out code that's needed to fully describe

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target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2011-06-24 01:44:41 +00:00
parent 66dddd1da3
commit a347f85dbe
52 changed files with 502 additions and 271 deletions
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5
lib/Target/Sparc/CMakeLists.txt
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@ -1,8 +1,9 @@
set(LLVM_TARGET_DEFINITIONS Sparc.td)
tablegen(SparcGenRegisterInfo.h.inc -gen-register-desc-header)
tablegen(SparcGenRegisterNames.inc -gen-register-enums)
tablegen(SparcGenRegisterInfo.inc -gen-register-desc)
tablegen(SparcGenRegisterDesc.inc -gen-register-desc)
tablegen(SparcGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(SparcGenRegisterInfo.inc -gen-register-info)
tablegen(SparcGenInstrNames.inc -gen-instr-enums)
tablegen(SparcGenInstrInfo.inc -gen-instr-desc)
tablegen(SparcGenAsmWriter.inc -gen-asm-writer)

3
lib/Target/Sparc/Makefile
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@ -13,7 +13,8 @@ TARGET = Sparc
# Make sure that tblgen is run, first thing.
BUILT_SOURCES = SparcGenRegisterInfo.h.inc SparcGenRegisterNames.inc \
SparcGenRegisterInfo.inc SparcGenInstrNames.inc \
SparcGenRegisterInfo.inc SparcGenRegisterDesc.inc \
SparcGenInstrNames.inc \
SparcGenInstrInfo.inc SparcGenAsmWriter.inc \
SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc

8
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@ -23,11 +23,14 @@
#include "llvm/Type.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#include "SparcGenRegisterDesc.inc"
#include "SparcGenRegisterInfo.inc"
using namespace llvm;
SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
const TargetInstrInfo &tii)
: SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
: SparcGenRegisterInfo(SparcRegDesc, SparcRegInfoDesc,
SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
Subtarget(st), TII(tii) {
}
@ -135,6 +138,3 @@ int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
int SparcRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
return SparcGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
}
#include "SparcGenRegisterInfo.inc"