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R600/SI: rework VOP1_* patterns v2
Fixing asm operation names. v2: use ZERO constant, also add asm operands Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175748 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -141,29 +141,33 @@ class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
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opName, pattern
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>;
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class VOP1_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
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string opName, list<dag> pattern> :
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VOP1 <
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op, (outs vrc:$dst), (ins arc:$src0), opName, pattern
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multiclass VOP1_Helper <bits<8> op, RegisterClass drc, RegisterClass src,
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string opName, list<dag> pattern> {
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def _e32: VOP1 <
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op, (outs drc:$dst), (ins src:$src0),
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opName#"_e32 $dst, $src0", pattern
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>;
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multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern> {
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def _e32: VOP1_Helper <op, VReg_32, VSrc_32, opName, pattern>;
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def _e64 : VOP3_32 <{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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opName, []
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>;
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}
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multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern> {
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def _e32 : VOP1_Helper <op, VReg_64, VSrc_64, opName, pattern>;
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def _e64 : VOP3_64 <
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def _e64 : VOP3 <
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{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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opName, []
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>;
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(outs drc:$dst),
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(ins src:$src0,
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i32imm:$abs, i32imm:$clamp,
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i32imm:$omod, i32imm:$neg),
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opName#"_e64 $dst, $src0, $abs, $clamp, $omod, $neg", []
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> {
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let SRC1 = SIOperand.ZERO;
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let SRC2 = SIOperand.ZERO;
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}
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}
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multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern>
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: VOP1_Helper <op, VReg_32, VSrc_32, opName, pattern>;
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multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern>
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: VOP1_Helper <op, VReg_64, VSrc_64, opName, pattern>;
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class VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
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string opName, list<dag> pattern> :
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VOP2 <
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