mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-08 18:30:04 +00:00
[Hexagon] Removing old def versions and replacing usages with versions that have encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223720 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
653ef32216
commit
a3b01e5189
@ -322,21 +322,21 @@ static unsigned doesIntrinsicContainPredicate(unsigned ID)
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case Intrinsic::hexagon_C2_tfrpr:
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return Hexagon::TFR_RsPd;
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case Intrinsic::hexagon_C2_and:
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return Hexagon::AND_pp;
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return Hexagon::C2_and;
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case Intrinsic::hexagon_C2_xor:
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return Hexagon::XOR_pp;
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return Hexagon::C2_xor;
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case Intrinsic::hexagon_C2_or:
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return Hexagon::OR_pp;
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return Hexagon::C2_or;
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case Intrinsic::hexagon_C2_not:
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return Hexagon::NOT_p;
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return Hexagon::C2_not;
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case Intrinsic::hexagon_C2_any8:
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return Hexagon::ANY_pp;
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return Hexagon::C2_any8;
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case Intrinsic::hexagon_C2_all8:
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return Hexagon::ALL_pp;
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return Hexagon::C2_all8;
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case Intrinsic::hexagon_C2_vitpack:
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return Hexagon::VITPACK_pp;
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return Hexagon::C2_vitpack;
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case Intrinsic::hexagon_C2_mask:
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return Hexagon::MASK_p;
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return Hexagon::C2_mask;
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case Intrinsic::hexagon_C2_mux:
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return Hexagon::C2_mux;
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@ -936,7 +936,7 @@ SDNode *HexagonDAGToDAGISel::SelectSelect(SDNode *N) {
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N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) {
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SDNode *SextNode = CurDAG->getMachineNode(Hexagon::A2_sxth, dl,
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MVT::i32, N000);
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SDNode *Result = CurDAG->getMachineNode(Hexagon::MAXw_rr, dl,
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SDNode *Result = CurDAG->getMachineNode(Hexagon::A2_max, dl,
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MVT::i32,
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SDValue(SextNode, 0),
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N1);
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@ -960,7 +960,7 @@ SDNode *HexagonDAGToDAGISel::SelectSelect(SDNode *N) {
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N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) {
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SDNode *SextNode = CurDAG->getMachineNode(Hexagon::A2_sxth, dl,
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MVT::i32, N000);
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SDNode *Result = CurDAG->getMachineNode(Hexagon::MINw_rr, dl,
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SDNode *Result = CurDAG->getMachineNode(Hexagon::A2_min, dl,
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MVT::i32,
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SDValue(SextNode, 0),
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N1);
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@ -1297,11 +1297,11 @@ SDNode *HexagonDAGToDAGISel::SelectConstant(SDNode *N) {
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SDValue(IntRegTFR, 0));
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// not(Pd)
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SDNode* NotPd = CurDAG->getMachineNode(Hexagon::NOT_p, dl, MVT::i1,
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SDNode* NotPd = CurDAG->getMachineNode(Hexagon::C2_not, dl, MVT::i1,
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SDValue(Pd, 0));
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// xor(not(Pd))
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Result = CurDAG->getMachineNode(Hexagon::XOR_pp, dl, MVT::i1,
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Result = CurDAG->getMachineNode(Hexagon::C2_xor, dl, MVT::i1,
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SDValue(Pd, 0), SDValue(NotPd, 0));
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// We have just built:
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@ -427,7 +427,7 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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}
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if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
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// Map Pd = Ps to Pd = or(Ps, Ps).
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BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
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BuildMI(MBB, I, DL, get(Hexagon::C2_or),
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DestReg).addReg(SrcReg).addReg(SrcReg);
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return;
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}
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@ -1179,106 +1179,6 @@ def: Pat<(i64 (and I64:$Rs, I64:$Rt)), (A2_andp I64:$Rs, I64:$Rt)>;
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def: Pat<(i64 (or I64:$Rs, I64:$Rt)), (A2_orp I64:$Rs, I64:$Rt)>;
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def: Pat<(i64 (xor I64:$Rs, I64:$Rt)), (A2_xorp I64:$Rs, I64:$Rt)>;
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def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
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DoubleRegs:$src2),
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"$dst = add($src1, $src2)",
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[(set (i64 DoubleRegs:$dst), (add (i64 DoubleRegs:$src1),
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(i64 DoubleRegs:$src2)))]>;
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// Logical operations.
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def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
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DoubleRegs:$src2),
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"$dst = and($src1, $src2)",
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[(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
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(i64 DoubleRegs:$src2)))]>;
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def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
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DoubleRegs:$src2),
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"$dst = or($src1, $src2)",
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[(set (i64 DoubleRegs:$dst), (or (i64 DoubleRegs:$src1),
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(i64 DoubleRegs:$src2)))]>;
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def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
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DoubleRegs:$src2),
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"$dst = xor($src1, $src2)",
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[(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
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(i64 DoubleRegs:$src2)))]>;
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// Maximum.
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def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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"$dst = max($src2, $src1)",
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[(set (i32 IntRegs:$dst),
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(i32 (select (i1 (setlt (i32 IntRegs:$src2),
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(i32 IntRegs:$src1))),
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(i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
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def MAXUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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"$dst = maxu($src2, $src1)",
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[(set (i32 IntRegs:$dst),
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(i32 (select (i1 (setult (i32 IntRegs:$src2),
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(i32 IntRegs:$src1))),
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(i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
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def MAXd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
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DoubleRegs:$src2),
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"$dst = max($src2, $src1)",
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[(set (i64 DoubleRegs:$dst),
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(i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
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(i64 DoubleRegs:$src1))),
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(i64 DoubleRegs:$src1),
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(i64 DoubleRegs:$src2))))]>;
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def MAXUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
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DoubleRegs:$src2),
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"$dst = maxu($src2, $src1)",
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[(set (i64 DoubleRegs:$dst),
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(i64 (select (i1 (setult (i64 DoubleRegs:$src2),
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(i64 DoubleRegs:$src1))),
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(i64 DoubleRegs:$src1),
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(i64 DoubleRegs:$src2))))]>;
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// Minimum.
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def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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"$dst = min($src2, $src1)",
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[(set (i32 IntRegs:$dst),
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(i32 (select (i1 (setgt (i32 IntRegs:$src2),
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(i32 IntRegs:$src1))),
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(i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
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def MINUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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"$dst = minu($src2, $src1)",
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[(set (i32 IntRegs:$dst),
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(i32 (select (i1 (setugt (i32 IntRegs:$src2),
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(i32 IntRegs:$src1))),
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(i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
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def MINd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
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DoubleRegs:$src2),
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"$dst = min($src2, $src1)",
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[(set (i64 DoubleRegs:$dst),
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(i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
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(i64 DoubleRegs:$src1))),
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(i64 DoubleRegs:$src1),
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(i64 DoubleRegs:$src2))))]>;
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def MINUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
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DoubleRegs:$src2),
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"$dst = minu($src2, $src1)",
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[(set (i64 DoubleRegs:$dst),
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(i64 (select (i1 (setugt (i64 DoubleRegs:$src2),
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(i64 DoubleRegs:$src1))),
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(i64 DoubleRegs:$src1),
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(i64 DoubleRegs:$src2))))]>;
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// Subtract.
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def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
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DoubleRegs:$src2),
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"$dst = sub($src1, $src2)",
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[(set (i64 DoubleRegs:$dst), (sub (i64 DoubleRegs:$src1),
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(i64 DoubleRegs:$src2)))]>;
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// Subtract halfword.
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//===----------------------------------------------------------------------===//
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// ALU64/ALU -
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//===----------------------------------------------------------------------===//
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@ -1393,29 +1293,6 @@ def C2_mask : SInst<(outs DoubleRegs:$Rd), (ins PredRegs:$Pt),
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let Inst{9-8} = Pt;
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let Inst{4-0} = Rd;
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}
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def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
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"$dst = and($src1, $src2)",
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[(set (i1 PredRegs:$dst), (and (i1 PredRegs:$src1),
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(i1 PredRegs:$src2)))]>;
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let hasSideEffects = 0 in
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def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
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PredRegs:$src2),
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"$dst = and($src1, !$src2)",
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[]>;
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def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
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"$dst = any8($src1)",
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[]>;
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def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
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"$dst = all8($src1)",
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[]>;
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def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
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PredRegs:$src2),
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"$dst = vitpack($src1, $src2)",
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[]>;
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def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
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DoubleRegs:$src2,
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@ -1429,25 +1306,6 @@ def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
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"$dst = vspliceb($src1, $src2, $src3)",
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[]>;
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def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
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"$dst = mask($src1)",
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[]>;
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def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
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"$dst = not($src1)",
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[(set (i1 PredRegs:$dst), (not (i1 PredRegs:$src1)))]>;
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def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
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"$dst = or($src1, $src2)",
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[(set (i1 PredRegs:$dst), (or (i1 PredRegs:$src1),
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(i1 PredRegs:$src2)))]>;
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def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
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"$dst = xor($src1, $src2)",
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[(set (i1 PredRegs:$dst), (xor (i1 PredRegs:$src1),
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(i1 PredRegs:$src2)))]>;
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// User control register transfer.
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//===----------------------------------------------------------------------===//
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// CR -
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@ -2861,7 +2719,7 @@ def : Pat <(and (i32 IntRegs:$src1), 255),
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// Add(p1, false) should never be produced,
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// if it does, it got to be mapped to NOOP.
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def : Pat <(add (i1 PredRegs:$src1), -1),
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(NOT_p (i1 PredRegs:$src1))>;
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(C2_not (i1 PredRegs:$src1))>;
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// Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
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def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
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@ -2887,7 +2745,7 @@ def : Pat <(brcond (not (i1 PredRegs:$src1)), bb:$offset),
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// Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
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def : Pat <(and (i1 PredRegs:$src1), (not (i1 PredRegs:$src2))),
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(i1 (AND_pnotp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
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(i1 (C2_andn (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
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let AddedComplexity = 100 in
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@ -2977,8 +2835,8 @@ def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
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// From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
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def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
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(i1 PredRegs:$src3)),
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(OR_pp (AND_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
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(AND_pp (NOT_p (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
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(C2_or (C2_and (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
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(C2_and (C2_not (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
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// Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
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def : Pat<(i1 (load ADDRriS11_2:$addr)),
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@ -3034,41 +2892,41 @@ def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
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// Map cmple -> cmpgt.
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// rs <= rt -> !(rs > rt).
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def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
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(i1 (NOT_p (C2_cmpgti (i32 IntRegs:$src1), s10ExtPred:$src2)))>;
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(i1 (C2_not (C2_cmpgti (i32 IntRegs:$src1), s10ExtPred:$src2)))>;
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// rs <= rt -> !(rs > rt).
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def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
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(i1 (NOT_p (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
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(i1 (C2_not (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
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// Rss <= Rtt -> !(Rss > Rtt).
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def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
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(i1 (NOT_p (C2_cmpgtp (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
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(i1 (C2_not (C2_cmpgtp (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
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// Map cmpne -> cmpeq.
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// Hexagon_TODO: We should improve on this.
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// rs != rt -> !(rs == rt).
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def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
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(i1 (NOT_p(i1 (C2_cmpeqi (i32 IntRegs:$src1), s10ExtPred:$src2))))>;
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(i1 (C2_not(i1 (C2_cmpeqi (i32 IntRegs:$src1), s10ExtPred:$src2))))>;
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// Map cmpne(Rs) -> !cmpeqe(Rs).
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// rs != rt -> !(rs == rt).
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def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
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(i1 (NOT_p (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
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(i1 (C2_not (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
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// Convert setne back to xor for hexagon since we compute w/ pred registers.
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def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
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(i1 (XOR_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
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(i1 (C2_xor (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
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// Map cmpne(Rss) -> !cmpew(Rss).
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// rs != rt -> !(rs == rt).
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def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
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(i1 (NOT_p (i1 (C2_cmpeqp (i64 DoubleRegs:$src1),
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(i1 (C2_not (i1 (C2_cmpeqp (i64 DoubleRegs:$src1),
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(i64 DoubleRegs:$src2)))))>;
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// Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
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// rs >= rt -> !(rt > rs).
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def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
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(i1 (NOT_p (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
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(i1 (C2_not (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
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// cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
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def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)),
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@ -3077,14 +2935,14 @@ def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)),
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// Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
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// rss >= rtt -> !(rtt > rss).
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def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
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(i1 (NOT_p (i1 (C2_cmpgtp (i64 DoubleRegs:$src2),
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(i1 (C2_not (i1 (C2_cmpgtp (i64 DoubleRegs:$src2),
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(i64 DoubleRegs:$src1)))))>;
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// Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
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// !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
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// rs < rt -> !(rs >= rt).
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def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
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(i1 (NOT_p (C2_cmpgti (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2))))>;
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(i1 (C2_not (C2_cmpgti (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2))))>;
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|
||||
// Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
|
||||
// rs < rt -> rt > rs.
|
||||
@ -3123,22 +2981,22 @@ def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)),
|
||||
// Map from Rs >= Rt -> !(Rt > Rs).
|
||||
// rs >= rt -> !(rt > rs).
|
||||
def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
|
||||
(i1 (NOT_p (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
|
||||
(i1 (C2_not (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
|
||||
|
||||
// Map from Rs >= Rt -> !(Rt > Rs).
|
||||
// rs >= rt -> !(rt > rs).
|
||||
def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
|
||||
(i1 (NOT_p (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
|
||||
(i1 (C2_not (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
|
||||
|
||||
// Map from cmpleu(Rs, Rt) -> !cmpgtu(Rs, Rt).
|
||||
// Map from (Rs <= Rt) -> !(Rs > Rt).
|
||||
def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
|
||||
(i1 (NOT_p (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
|
||||
(i1 (C2_not (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
|
||||
|
||||
// Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
|
||||
// Map from (Rs <= Rt) -> !(Rs > Rt).
|
||||
def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
|
||||
(i1 (NOT_p (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
|
||||
(i1 (C2_not (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
|
||||
|
||||
// Sign extends.
|
||||
// i1 -> i32
|
||||
|
||||
@ -290,36 +290,36 @@ def : Pat<(i1 (setule (f64 DoubleRegs:$src1), (fpimm:$src2))),
|
||||
|
||||
// ne.
|
||||
def : Pat<(i1 (setone (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
|
||||
(i1 (NOT_p (FCMPOEQ32_rr IntRegs:$src1, IntRegs:$src2)))>,
|
||||
(i1 (C2_not (FCMPOEQ32_rr IntRegs:$src1, IntRegs:$src2)))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat<(i1 (setone (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
|
||||
(i1 (NOT_p (FCMPOEQ64_rr DoubleRegs:$src1, DoubleRegs:$src2)))>,
|
||||
(i1 (C2_not (FCMPOEQ64_rr DoubleRegs:$src1, DoubleRegs:$src2)))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat<(i1 (setune (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
|
||||
(i1 (NOT_p (FCMPUEQ32_rr IntRegs:$src1, IntRegs:$src2)))>,
|
||||
(i1 (C2_not (FCMPUEQ32_rr IntRegs:$src1, IntRegs:$src2)))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat<(i1 (setune (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
|
||||
(i1 (NOT_p (FCMPUEQ64_rr DoubleRegs:$src1, DoubleRegs:$src2)))>,
|
||||
(i1 (C2_not (FCMPUEQ64_rr DoubleRegs:$src1, DoubleRegs:$src2)))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat<(i1 (setone (f32 IntRegs:$src1), (fpimm:$src2))),
|
||||
(i1 (NOT_p (FCMPOEQ32_rr IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
|
||||
(i1 (C2_not (FCMPOEQ32_rr IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat<(i1 (setone (f64 DoubleRegs:$src1), (fpimm:$src2))),
|
||||
(i1 (NOT_p (FCMPOEQ64_rr DoubleRegs:$src1,
|
||||
(i1 (C2_not (FCMPOEQ64_rr DoubleRegs:$src1,
|
||||
(f64 (CONST64_Float_Real fpimm:$src2)))))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat<(i1 (setune (f32 IntRegs:$src1), (fpimm:$src2))),
|
||||
(i1 (NOT_p (FCMPUEQ32_rr IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
|
||||
(i1 (C2_not (FCMPUEQ32_rr IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat<(i1 (setune (f64 DoubleRegs:$src1), (fpimm:$src2))),
|
||||
(i1 (NOT_p (FCMPUEQ64_rr DoubleRegs:$src1,
|
||||
(i1 (C2_not (FCMPUEQ64_rr DoubleRegs:$src1,
|
||||
(f64 (CONST64_Float_Real fpimm:$src2)))))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
|
||||
@ -184,7 +184,7 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
|
||||
|
||||
// Look for P=NOT(P).
|
||||
if (!DisablePNotP &&
|
||||
(MI->getOpcode() == Hexagon::NOT_p)) {
|
||||
(MI->getOpcode() == Hexagon::C2_not)) {
|
||||
assert (MI->getNumOperands() == 2);
|
||||
MachineOperand &Dst = MI->getOperand(0);
|
||||
MachineOperand &Src = MI->getOperand(1);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user