6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-04-09 16:45:03 +00:00
Code Issues Projects Releases Wiki Activity

Added MIPS changes to release notes for 3.5.2.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@232369 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2015-03-16 10:40:59 +00:00
parent 0cf4dc1701
commit a3bab355fb
1 changed files with 22 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
docs/ReleaseNotes.rst
View File

@ -27,6 +27,28 @@ Non-comprehensive list of changes in this release
Changes to the MIPS Target
--------------------------
* Corrected inline assembly to use the same assembler options as GCC for the
duration of the inline assembly block. Particularly, ``.set reorder``,
``.set nomacro``, and ``.set noat`` are now correct.
* Added ability to specify $gp as a named register global variable.
* Added support for ``.set push`` and ``.set pop``.
* Fixed a code generation bug in the comparison operators for MIPS32r6/MIPS64r6
where the compiler would use ``<`` when it should have used ``<=``.
* Fixed various assertions when using 128-bit integers on 64-bit targets.
* Fixed invalid use of an odd-numbered single-precision floating point register
when using ``-mno-odd-spreg`` with ``-msa``.
Non-comprehensive list of changes in 3.5.1
==========================================
Changes to the MIPS Target
--------------------------
* A large number of bugs have been fixed for big-endian Mips targets using the
N32 and N64 ABI's. Please note that some of these bugs will still affect
LLVM-IR generated by LLVM 3.5 since correct code generation depends on