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[AArch64]Fix an assertion failure in DAG Combiner about concating 2 build_vector.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212677 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hao Liu 2014-07-10 03:41:50 +00:00
parent 425ef825a6
commit a3c15c19b8
2 changed files with 33 additions and 5 deletions
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22
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -10390,10 +10390,24 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
SmallVector<SDValue, 8> Opnds;
unsigned BuildVecNumElts = N0.getNumOperands();
for (unsigned i = 0; i != BuildVecNumElts; ++i)
Opnds.push_back(N0.getOperand(i));
for (unsigned i = 0; i != BuildVecNumElts; ++i)
Opnds.push_back(N1.getOperand(i));
EVT SclTy0 = N0.getOperand(0)->getValueType(0);
EVT SclTy1 = N1.getOperand(0)->getValueType(0);
if (SclTy0.isFloatingPoint()) {
for (unsigned i = 0; i != BuildVecNumElts; ++i)
Opnds.push_back(N0.getOperand(i));
for (unsigned i = 0; i != BuildVecNumElts; ++i)
Opnds.push_back(N1.getOperand(i));
} else {
// If BUILD_VECTOR are from built from integer, they may have different
// operand types. Get the smaller type and truncate all operands to it.
EVT MinTy = SclTy0.bitsLE(SclTy1) ? SclTy0 : SclTy1;
for (unsigned i = 0; i != BuildVecNumElts; ++i)
Opnds.push_back(DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinTy,
N0.getOperand(i)));
for (unsigned i = 0; i != BuildVecNumElts; ++i)
Opnds.push_back(DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinTy,
N1.getOperand(i)));
}
return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
}

16
test/CodeGen/AArch64/arm64-build-vector.ll
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@ -42,4 +42,18 @@ define <8 x i16> @build_all_zero(<8 x i16> %a) #1 {
%b = add <8 x i16> %a, <i16 -32768, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>
%c = mul <8 x i16> %b, <i16 -20864, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>
ret <8 x i16> %c
}
}
; There is an optimization in DAG Combiner as following:
; fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...))
; -> (BUILD_VECTOR A, B, ..., C, D, ...)
; This case checks when A,B and C,D are different types, there should be no
; assertion failure.
define <8 x i16> @concat_2_build_vector(<4 x i16> %in0) {
; CHECK-LABEL: concat_2_build_vector:
; CHECK: movi
%vshl_n = shl <4 x i16> %in0, <i16 8, i16 8, i16 8, i16 8>
%vshl_n2 = shl <4 x i16> %vshl_n, <i16 9, i16 9, i16 9, i16 9>
%shuffle.i = shufflevector <4 x i16> %vshl_n2, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i16> %shuffle.i
}