diff --git a/include/llvm/Target/MRegisterInfo.h b/include/llvm/Target/MRegisterInfo.h index a4846d8afa8..dab5d20b3c2 100644 --- a/include/llvm/Target/MRegisterInfo.h +++ b/include/llvm/Target/MRegisterInfo.h @@ -70,6 +70,7 @@ private: const sc_iterator SubRegClasses; const sc_iterator SuperRegClasses; const unsigned RegSize, Alignment; // Size & Alignment of register in bytes + const int CopyCost; const iterator RegsBegin, RegsEnd; public: TargetRegisterClass(unsigned id, @@ -78,10 +79,11 @@ public: const TargetRegisterClass * const *supcs, const TargetRegisterClass * const *subregcs, const TargetRegisterClass * const *superregcs, - unsigned RS, unsigned Al, iterator RB, iterator RE) + unsigned RS, unsigned Al, int CC, + iterator RB, iterator RE) : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs), SubRegClasses(subregcs), SuperRegClasses(superregcs), - RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {} + RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {} virtual ~TargetRegisterClass() {} // Allow subclasses /// getID() - Return the register class ID number. @@ -258,6 +260,10 @@ public: /// getAlignment - Return the minimum required alignment for a register of /// this class. unsigned getAlignment() const { return Alignment; } + + /// getCopyCost - Return the cost of copying a value between two registers in + /// this class. + int getCopyCost() const { return CopyCost; } }; diff --git a/lib/Target/Target.td b/lib/Target/Target.td index 4e495fb75cd..15213ce2831 100644 --- a/lib/Target/Target.td +++ b/lib/Target/Target.td @@ -104,6 +104,12 @@ class RegisterClass regTypes, int alignment, // int Alignment = alignment; + // CopyCost - This value is used to specify the cost of copying a value + // between two registers in this register class. The default value is one + // meaning it takes a single instruction to perform the copying. A negative + // value means copying is extremely expensive or impossible. + int CopyCost = 1; + // MemberList - Specify which registers are in this class. If the // allocation_order_* method are not specified, this also defines the order of // allocation used by the register allocator. diff --git a/utils/TableGen/CodeGenRegisters.h b/utils/TableGen/CodeGenRegisters.h index cee81e9092c..a5636e34f21 100644 --- a/utils/TableGen/CodeGenRegisters.h +++ b/utils/TableGen/CodeGenRegisters.h @@ -38,6 +38,7 @@ namespace llvm { std::vector VTs; unsigned SpillSize; unsigned SpillAlignment; + int CopyCost; std::vector SubRegClasses; std::string MethodProtos, MethodBodies; diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp index 1fee306e9f8..c73ffb98ef1 100644 --- a/utils/TableGen/CodeGenTarget.cpp +++ b/utils/TableGen/CodeGenTarget.cpp @@ -221,6 +221,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) { Namespace = R->getValueAsString("Namespace"); SpillSize = Size ? Size : MVT::getSizeInBits(VTs[0]); SpillAlignment = R->getValueAsInt("Alignment"); + CopyCost = R->getValueAsInt("CopyCost"); MethodBodies = R->getValueAsCode("MethodBodies"); MethodProtos = R->getValueAsCode("MethodProtos"); } diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index 06c575da3ae..2f948afa3de 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -384,8 +384,10 @@ void RegisterInfoEmitter::run(std::ostream &OS) { << RC.getName() + "SubRegClasses" << ", " << RC.getName() + "SuperRegClasses" << ", " << RC.SpillSize/8 << ", " - << RC.SpillAlignment/8 << ", " << RC.getName() << ", " - << RC.getName() << " + " << RC.Elements.size() << ") {}\n"; + << RC.SpillAlignment/8 << ", " + << RC.CopyCost << ", " + << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size() + << ") {}\n"; } OS << "}\n";