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Support BufferSize on ProcResGroup for unified MOp schedulers.

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And add Sandybridge/Haswell resource buffers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184034 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick
2013-06-15 04:50:06 +00:00
parent a5ce5f36d3
commit a3d82ce19f
6 changed files with 30 additions and 6 deletions
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1
include/llvm/Target/TargetSchedule.td
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@ -138,6 +138,7 @@ class ProcResource<int num> : ProcResourceKind,
class ProcResGroup<list<ProcResource> resources> : ProcResourceKind { class ProcResGroup<list<ProcResource> resources> : ProcResourceKind {
list<ProcResource> Resources = resources; list<ProcResource> Resources = resources;
SchedMachineModel SchedModel = ?; SchedMachineModel SchedModel = ?;
int BufferSize = -1;
} }
// A target architecture may define SchedReadWrite types and associate // A target architecture may define SchedReadWrite types and associate

6
lib/Target/X86/X86SchedHaswell.td
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@ -49,6 +49,12 @@ def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>;
def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>; def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>;
def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>; def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>;
// 60 Entry Unified Scheduler
def HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4,
HWPort5, HWPort6, HWPort7]> {
let BufferSize=60;
}
// Integer division issued on port 0. // Integer division issued on port 0.
def HWDivider : ProcResource<1>; def HWDivider : ProcResource<1>;

5
lib/Target/X86/X86SchedSandyBridge.td
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@ -45,6 +45,11 @@ def SBPort05 : ProcResGroup<[SBPort0, SBPort5]>;
def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>;
def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;
// 54 Entry Unified Scheduler
def SBPortAny : ProcResGroup<[SBPort0, SBPort1, SBPort23, SBPort4, SBPort5]> {
let BufferSize=54;
}
// Integer division issued on port 0. // Integer division issued on port 0.
def SBDivider : ProcResource<1>; def SBDivider : ProcResource<1>;

13
utils/TableGen/CodeGenSchedule.cpp
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@ -1476,6 +1476,19 @@ void CodeGenSchedModels::collectProcResources() {
Record *ModelDef = (*RAI)->getValueAsDef("SchedModel"); Record *ModelDef = (*RAI)->getValueAsDef("SchedModel");
addReadAdvance(*RAI, getProcModel(ModelDef).Index); addReadAdvance(*RAI, getProcModel(ModelDef).Index);
} }
// Add ProcResGroups that are defined within this processor model, which may
// not be directly referenced but may directly specify a buffer size.
RecVec ProcResGroups = Records.getAllDerivedDefinitions("ProcResGroup");
for (RecIter RI = ProcResGroups.begin(), RE = ProcResGroups.end();
RI != RE; ++RI) {
if (!(*RI)->getValueInit("SchedModel")->isComplete())
continue;
CodeGenProcModel &PM = getProcModel((*RI)->getValueAsDef("SchedModel"));
RecIter I = std::find(PM.ProcResourceDefs.begin(),
PM.ProcResourceDefs.end(), *RI);
if (I == PM.ProcResourceDefs.end())
PM.ProcResourceDefs.push_back(*RI);
}
// Finalize each ProcModel by sorting the record arrays. // Finalize each ProcModel by sorting the record arrays.
for (unsigned PIdx = 0, PEnd = ProcModels.size(); PIdx != PEnd; ++PIdx) { for (unsigned PIdx = 0, PEnd = ProcModels.size(); PIdx != PEnd; ++PIdx) {
CodeGenProcModel &PM = ProcModels[PIdx]; CodeGenProcModel &PM = ProcModels[PIdx];

5
utils/TableGen/CodeGenSchedule.h
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@ -266,11 +266,14 @@ public:
return ProcModels[I->second]; return ProcModels[I->second];
} }
const CodeGenProcModel &getProcModel(Record *ModelDef) const { CodeGenProcModel &getProcModel(Record *ModelDef) {
ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef); ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
assert(I != ProcModelMap.end() && "missing machine model"); assert(I != ProcModelMap.end() && "missing machine model");
return ProcModels[I->second]; return ProcModels[I->second];
} }
const CodeGenProcModel &getProcModel(Record *ModelDef) const {
return const_cast<CodeGenSchedModels*>(this)->getProcModel(ModelDef);
}
// Iterate over the unique processor models. // Iterate over the unique processor models.
typedef std::vector<CodeGenProcModel>::const_iterator ProcIter; typedef std::vector<CodeGenProcModel>::const_iterator ProcIter;

6
utils/TableGen/SubtargetEmitter.cpp
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@ -634,14 +634,11 @@ void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,
Record *SuperDef = 0; Record *SuperDef = 0;
unsigned SuperIdx = 0; unsigned SuperIdx = 0;
unsigned NumUnits = 0; unsigned NumUnits = 0;
int BufferSize = -1; int BufferSize = PRDef->getValueAsInt("BufferSize");
if (PRDef->isSubClassOf("ProcResGroup")) { if (PRDef->isSubClassOf("ProcResGroup")) {
RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources");
for (RecIter RUI = ResUnits.begin(), RUE = ResUnits.end(); for (RecIter RUI = ResUnits.begin(), RUE = ResUnits.end();
RUI != RUE; ++RUI) { RUI != RUE; ++RUI) {
int BuffSz = (*RUI)->getValueAsInt("BufferSize");
if (!NumUnits || (unsigned)BufferSize < (unsigned)BuffSz)
BufferSize = BuffSz;
NumUnits += (*RUI)->getValueAsInt("NumUnits"); NumUnits += (*RUI)->getValueAsInt("NumUnits");
} }
} }
@ -653,7 +650,6 @@ void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,
SuperIdx = ProcModel.getProcResourceIdx(SuperDef); SuperIdx = ProcModel.getProcResourceIdx(SuperDef);
} }
NumUnits = PRDef->getValueAsInt("NumUnits"); NumUnits = PRDef->getValueAsInt("NumUnits");
BufferSize = PRDef->getValueAsInt("BufferSize");
} }
// Emit the ProcResourceDesc // Emit the ProcResourceDesc
if (i+1 == e) if (i+1 == e)