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https://github.com/c64scene-ar/llvm-6502.git
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Tidy up trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161027 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
5592b4567d
commit
a40476f9cc
@ -19,17 +19,17 @@
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define INSTRUCTION_SPECIFIER_FIELDS
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#define INSTRUCTION_IDS \
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unsigned instructionIDs;
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#include "X86DisassemblerDecoderCommon.h"
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#undef INSTRUCTION_SPECIFIER_FIELDS
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#undef INSTRUCTION_IDS
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/*
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* Accessor functions for various fields of an Intel instruction
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*/
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@ -43,7 +43,7 @@ extern "C" {
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#define rFromREX(rex) (((rex) & 0x4) >> 2)
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#define xFromREX(rex) (((rex) & 0x2) >> 1)
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#define bFromREX(rex) ((rex) & 0x1)
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#define rFromVEX2of3(vex) (((~(vex)) & 0x80) >> 7)
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#define xFromVEX2of3(vex) (((~(vex)) & 0x40) >> 6)
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#define bFromVEX2of3(vex) (((~(vex)) & 0x20) >> 5)
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@ -237,7 +237,7 @@ extern "C" {
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ENTRY(YMM13) \
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ENTRY(YMM14) \
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ENTRY(YMM15)
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#define REGS_SEGMENT \
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ENTRY(ES) \
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ENTRY(CS) \
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@ -245,7 +245,7 @@ extern "C" {
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ENTRY(DS) \
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ENTRY(FS) \
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ENTRY(GS)
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#define REGS_DEBUG \
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ENTRY(DR0) \
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ENTRY(DR1) \
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@ -266,12 +266,12 @@ extern "C" {
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ENTRY(CR6) \
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ENTRY(CR7) \
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ENTRY(CR8)
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#define ALL_EA_BASES \
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EA_BASES_16BIT \
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EA_BASES_32BIT \
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EA_BASES_64BIT
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#define ALL_SIB_BASES \
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REGS_32BIT \
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REGS_64BIT
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@ -290,7 +290,7 @@ extern "C" {
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ENTRY(RIP)
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/*
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* EABase - All possible values of the base field for effective-address
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* EABase - All possible values of the base field for effective-address
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* computations, a.k.a. the Mod and R/M fields of the ModR/M byte. We
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* distinguish between bases (EA_BASE_*) and registers that just happen to be
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* referred to when Mod == 0b11 (EA_REG_*).
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@ -305,8 +305,8 @@ typedef enum {
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#undef ENTRY
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EA_max
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} EABase;
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/*
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/*
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* SIBIndex - All possible values of the SIB index field.
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* Borrows entries from ALL_EA_BASES with the special case that
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* sib is synonymous with NONE.
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@ -321,7 +321,7 @@ typedef enum {
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#undef ENTRY
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SIB_INDEX_max
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} SIBIndex;
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/*
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* SIBBase - All possible values of the SIB base field.
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*/
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@ -353,7 +353,7 @@ typedef enum {
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#undef ENTRY
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MODRM_REG_max
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} Reg;
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/*
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* SegmentOverride - All possible segment overrides.
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*/
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@ -367,7 +367,7 @@ typedef enum {
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SEG_OVERRIDE_GS,
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SEG_OVERRIDE_max
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} SegmentOverride;
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/*
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* VEXLeadingOpcodeByte - Possible values for the VEX.m-mmmm field
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*/
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@ -431,16 +431,16 @@ struct InternalInstruction {
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void* dlogArg;
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/* General instruction information */
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/* The mode to disassemble for (64-bit, protected, real) */
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DisassemblerMode mode;
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/* The start of the instruction, usable with the reader */
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uint64_t startLocation;
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/* The length of the instruction, in bytes */
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size_t length;
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/* Prefix state */
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/* 1 if the prefix byte corresponding to the entry is present; 0 if not */
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uint8_t prefixPresent[0x100];
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/* contains the location (for use with the reader) of the prefix byte */
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@ -456,7 +456,7 @@ struct InternalInstruction {
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uint64_t necessaryPrefixLocation;
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/* The segment override type */
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SegmentOverride segmentOverride;
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/* Sizes of various critical pieces of data, in bytes */
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uint8_t registerSize;
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uint8_t addressSize;
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@ -467,9 +467,9 @@ struct InternalInstruction {
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needed to find relocation entries for adding symbolic operands */
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uint8_t displacementOffset;
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uint8_t immediateOffset;
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/* opcode state */
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/* The value of the two-byte escape prefix (usually 0x0f) */
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uint8_t twoByteEscape;
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/* The value of the three-byte escape prefix (usually 0x38 or 0x3a) */
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@ -478,16 +478,16 @@ struct InternalInstruction {
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uint8_t opcode;
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/* The ModR/M byte of the instruction, if it is an opcode extension */
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uint8_t modRMExtension;
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/* decode state */
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/* The type of opcode, used for indexing into the array of decode tables */
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OpcodeType opcodeType;
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/* The instruction ID, extracted from the decode table */
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uint16_t instructionID;
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/* The specifier for the instruction, from the instruction info table */
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const struct InstructionSpecifier *spec;
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/* state for additional bytes, consumed during operand decode. Pattern:
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consumed___ indicates that the byte was already consumed and does not
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need to be consumed again */
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@ -495,12 +495,12 @@ struct InternalInstruction {
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/* The VEX.vvvv field, which contains a third register operand for some AVX
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instructions */
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Reg vvvv;
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/* The ModR/M byte, which contains most register operands and some portion of
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all memory operands */
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BOOL consumedModRM;
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uint8_t modRM;
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/* The SIB byte, used for more complex 32- or 64-bit memory operands */
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BOOL consumedSIB;
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uint8_t sib;
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@ -508,19 +508,19 @@ struct InternalInstruction {
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/* The displacement, used for memory operands */
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BOOL consumedDisplacement;
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int32_t displacement;
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/* Immediates. There can be two in some cases */
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uint8_t numImmediatesConsumed;
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uint8_t numImmediatesTranslated;
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uint64_t immediates[2];
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/* A register or immediate operand encoded into the opcode */
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BOOL consumedOpcodeModifier;
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uint8_t opcodeModifier;
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Reg opcodeRegister;
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/* Portions of the ModR/M byte */
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/* These fields determine the allowable values for the ModR/M fields, which
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depend on operand and address widths */
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EABase eaBaseBase;
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@ -533,7 +533,7 @@ struct InternalInstruction {
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EADisplacement eaDisplacement;
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/* The reg field always encodes a register */
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Reg reg;
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/* SIB state */
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SIBIndex sibIndex;
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uint8_t sibScale;
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@ -571,15 +571,15 @@ int decodeInstruction(struct InternalInstruction* insn,
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* @param line - The line number that printed the debug message.
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* @param s - The message to print.
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*/
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void x86DisassemblerDebug(const char *file,
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unsigned line,
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const char *s);
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const char *x86DisassemblerGetInstrName(unsigned Opcode, void *mii);
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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#endif
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#endif
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