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[Hexagon] Patterns for frame index with offset for isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235418 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -60,6 +60,7 @@ def BITPOS32 : SDNodeXForm<imm, [{
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return XformMskToBitPosU5Imm(imm);
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return XformMskToBitPosU5Imm(imm);
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}]>;
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}]>;
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// Hexagon V4 Architecture spec defines 8 instruction classes:
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// Hexagon V4 Architecture spec defines 8 instruction classes:
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// LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
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// LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
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// compiler)
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// compiler)
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29
test/CodeGen/Hexagon/mem-fi-add.ll
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29
test/CodeGen/Hexagon/mem-fi-add.ll
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@ -0,0 +1,29 @@
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; RUN: llc -O2 < %s | FileCheck %s
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; Look for four stores directly via r29.
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; CHECK: memd(r29
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; CHECK: memd(r29
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; CHECK: memd(r29
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; CHECK: memd(r29
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target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
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target triple = "hexagon"
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; Function Attrs: nounwind
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define void @foo() #0 {
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entry:
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%t = alloca [4 x [2 x i32]], align 8
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%0 = bitcast [4 x [2 x i32]]* %t to i8*
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call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 32, i32 8, i1 false)
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%arraydecay = getelementptr inbounds [4 x [2 x i32]], [4 x [2 x i32]]* %t, i32 0, i32 0
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call void @bar([2 x i32]* %arraydecay) #1
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ret void
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}
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; Function Attrs: nounwind
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declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) #1
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declare void @bar([2 x i32]*) #2
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind }
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attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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