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Fix FastISel to not initialize the PIC-base register multiple times
in functions with PIC references from more than one basic block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56807 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -60,6 +60,7 @@ public:
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///
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void setCurrentBlock(MachineBasicBlock *mbb) {
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MBB = mbb;
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LocalValueMap.clear();
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}
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/// SelectInstruction - Do "fast" instruction selection for the given
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@ -709,6 +709,15 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
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void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
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MachineModuleInfo *MMI) {
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// Initialize the Fast-ISel state, if needed.
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FastISel *FastIS = 0;
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if (EnableFastISel)
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FastIS = TLI.createFastISel(*FuncInfo->MF, MMI,
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FuncInfo->ValueMap,
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FuncInfo->MBBMap,
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FuncInfo->StaticAllocaMap);
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// Iterate over all basic blocks in the function.
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for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
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BasicBlock *LLVMBB = &*I;
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BB = FuncInfo->MBBMap[LLVMBB];
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@ -724,7 +733,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
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// If any of the arguments has the byval attribute, forgo
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// fast-isel in the entry block.
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if (EnableFastISel) {
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if (FastIS) {
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unsigned j = 1;
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for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
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I != E; ++I, ++j)
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@ -739,74 +748,68 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
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// Before doing SelectionDAG ISel, see if FastISel has been requested.
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// FastISel doesn't support EH landing pads, which require special handling.
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if (EnableFastISel && !SuppressFastISel && !BB->isLandingPad()) {
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if (FastISel *F = TLI.createFastISel(*FuncInfo->MF, MMI,
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FuncInfo->ValueMap,
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FuncInfo->MBBMap,
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FuncInfo->StaticAllocaMap)) {
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// Emit code for any incoming arguments. This must happen before
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// beginning FastISel on the entry block.
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if (LLVMBB == &Fn.getEntryBlock()) {
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CurDAG->setRoot(SDL->getControlRoot());
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CodeGenAndEmitDAG();
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SDL->clear();
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}
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F->setCurrentBlock(BB);
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// Do FastISel on as many instructions as possible.
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for (; BI != End; ++BI) {
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// Just before the terminator instruction, insert instructions to
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// feed PHI nodes in successor blocks.
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if (isa<TerminatorInst>(BI))
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if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, F)) {
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if (EnableFastISelVerbose || EnableFastISelAbort) {
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cerr << "FastISel miss: ";
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BI->dump();
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}
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if (EnableFastISelAbort)
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assert(0 && "FastISel didn't handle a PHI in a successor");
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break;
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}
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// First try normal tablegen-generated "fast" selection.
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if (F->SelectInstruction(BI))
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continue;
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// Next, try calling the target to attempt to handle the instruction.
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if (F->TargetSelectInstruction(BI))
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continue;
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// Then handle certain instructions as single-LLVM-Instruction blocks.
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if (isa<CallInst>(BI)) {
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if (EnableFastISelVerbose || EnableFastISelAbort) {
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cerr << "FastISel missed call: ";
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BI->dump();
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}
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if (BI->getType() != Type::VoidTy) {
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unsigned &R = FuncInfo->ValueMap[BI];
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if (!R)
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R = FuncInfo->CreateRegForValue(BI);
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}
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SelectBasicBlock(LLVMBB, BI, next(BI));
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continue;
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}
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// Otherwise, give up on FastISel for the rest of the block.
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// For now, be a little lenient about non-branch terminators.
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if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
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if (FastIS && !SuppressFastISel && !BB->isLandingPad()) {
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// Emit code for any incoming arguments. This must happen before
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// beginning FastISel on the entry block.
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if (LLVMBB == &Fn.getEntryBlock()) {
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CurDAG->setRoot(SDL->getControlRoot());
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CodeGenAndEmitDAG();
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SDL->clear();
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}
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FastIS->setCurrentBlock(BB);
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// Do FastISel on as many instructions as possible.
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for (; BI != End; ++BI) {
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// Just before the terminator instruction, insert instructions to
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// feed PHI nodes in successor blocks.
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if (isa<TerminatorInst>(BI))
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if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
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if (EnableFastISelVerbose || EnableFastISelAbort) {
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cerr << "FastISel miss: ";
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BI->dump();
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}
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if (EnableFastISelAbort)
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// The "fast" selector couldn't handle something and bailed.
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// For the purpose of debugging, just abort.
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assert(0 && "FastISel didn't select the entire block");
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assert(0 && "FastISel didn't handle a PHI in a successor");
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break;
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}
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break;
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// First try normal tablegen-generated "fast" selection.
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if (FastIS->SelectInstruction(BI))
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continue;
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// Next, try calling the target to attempt to handle the instruction.
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if (FastIS->TargetSelectInstruction(BI))
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continue;
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// Then handle certain instructions as single-LLVM-Instruction blocks.
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if (isa<CallInst>(BI)) {
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if (EnableFastISelVerbose || EnableFastISelAbort) {
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cerr << "FastISel missed call: ";
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BI->dump();
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}
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if (BI->getType() != Type::VoidTy) {
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unsigned &R = FuncInfo->ValueMap[BI];
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if (!R)
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R = FuncInfo->CreateRegForValue(BI);
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}
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SelectBasicBlock(LLVMBB, BI, next(BI));
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continue;
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}
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delete F;
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// Otherwise, give up on FastISel for the rest of the block.
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// For now, be a little lenient about non-branch terminators.
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if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
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if (EnableFastISelVerbose || EnableFastISelAbort) {
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cerr << "FastISel miss: ";
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BI->dump();
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}
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if (EnableFastISelAbort)
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// The "fast" selector couldn't handle something and bailed.
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// For the purpose of debugging, just abort.
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assert(0 && "FastISel didn't select the entire block");
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}
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break;
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}
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}
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@ -818,6 +821,8 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
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FinishBasicBlock();
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}
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delete FastIS;
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}
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void
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