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Detect need for autoalignment of the stack earlier to catch spills more
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode 6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88874 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -109,6 +109,7 @@ FunctionPass *createNEONPreAllocPass();
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FunctionPass *createNEONMoveFixPass();
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FunctionPass *createThumb2ITBlockPass();
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FunctionPass *createThumb2SizeReductionPass();
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FunctionPass *createARMMaxStackAlignmentCalculatorPass();
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extern Target TheARMTarget, TheThumbTarget;
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@ -1132,6 +1132,7 @@ bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
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break;
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}
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case ARMII::AddrMode4:
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case ARMII::AddrMode6:
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// Can't fold any offset even if it's zero.
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return false;
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case ARMII::AddrMode5: {
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@ -1170,7 +1170,8 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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// as much as possible above, handle the rest, providing a register that is
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// SP+LargeImm.
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assert((Offset ||
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(MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4) &&
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(MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
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(MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
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"This code isn't needed if offset already handled!");
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unsigned ScratchReg = 0;
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@ -1179,7 +1180,7 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
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unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
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if (Offset == 0)
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// Must be addrmode4.
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// Must be addrmode4/6.
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MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
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else {
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ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
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@ -1462,4 +1463,46 @@ emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
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}
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namespace {
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struct MSAC : public MachineFunctionPass {
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static char ID;
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MSAC() : MachineFunctionPass(&ID) {}
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virtual bool runOnMachineFunction(MachineFunction &MF) {
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MachineFrameInfo *FFI = MF.getFrameInfo();
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MachineRegisterInfo &RI = MF.getRegInfo();
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// Calculate max stack alignment of all already allocated stack objects.
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unsigned MaxAlign = calculateMaxStackAlignment(FFI);
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// Be over-conservative: scan over all vreg defs and find, whether vector
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// registers are used. If yes - there is probability, that vector register
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// will be spilled and thus stack needs to be aligned properly.
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for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
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RegNum < RI.getLastVirtReg(); ++RegNum)
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MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
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if (FFI->getMaxAlignment() == MaxAlign)
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return false;
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FFI->setMaxAlignment(MaxAlign);
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return true;
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}
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virtual const char *getPassName() const {
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return "ARM Maximal Stack Alignment Calculator";
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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char MSAC::ID = 0;
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}
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FunctionPass*
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llvm::createARMMaxStackAlignmentCalculatorPass() { return new MSAC(); }
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#include "ARMGenRegisterInfo.inc"
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@ -93,6 +93,10 @@ bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
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if (Subtarget.hasNEON())
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PM.add(createNEONPreAllocPass());
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// Calculate and set max stack object alignment early, so we can decide
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// whether we will need stack realignment (and thus FP).
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PM.add(createARMMaxStackAlignmentCalculatorPass());
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// FIXME: temporarily disabling load / store optimization pass for Thumb1.
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if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
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PM.add(createARMLoadStoreOptimizationPass(true));
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@ -11,8 +11,9 @@ declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly
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define arm_apcscc void @aaa(%quuz* %this, i8* %block) {
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; CHECK: aaa:
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; CHECK: vstmia sp
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; CHECK: vldmia sp
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; CHECK: bic sp, sp, #15
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; CHECK: vst1.64 {{.*}}sp @128
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; CHECK: vld1.64 {{.*}}sp @128
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entry:
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%0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef) nounwind ; <<4 x float>> [#uses=1]
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store float 6.300000e+01, float* undef, align 4
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@ -11,8 +11,9 @@ declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly
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define arm_apcscc void @aaa(%quuz* %this, i8* %block) {
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; CHECK: aaa:
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; CHECK: vstmia sp
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; CHECK: vldmia sp
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; CHECK: bic sp, sp, #15
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; CHECK: vst1.64 {{.*}}sp @128
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; CHECK: vld1.64 {{.*}}sp @128
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entry:
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%0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef) nounwind ; <<4 x float>> [#uses=1]
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store float 6.300000e+01, float* undef, align 4
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