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Replace some std::vectors that showed up in heap profiling with
SmallVectors. Change the signature of TargetLowering::LowerArguments to avoid returning a vector by value, and update the two targets which still use this directly, Sparc and IA64, accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52917 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -964,8 +964,9 @@ public:
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/// LowerArguments - This hook must be implemented to indicate how we should
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/// LowerArguments - This hook must be implemented to indicate how we should
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/// lower the arguments for the specified function, into the specified DAG.
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/// lower the arguments for the specified function, into the specified DAG.
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virtual std::vector<SDOperand>
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virtual void
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LowerArguments(Function &F, SelectionDAG &DAG);
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LowerArguments(Function &F, SelectionDAG &DAG,
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SmallVectorImpl<SDOperand>& ArgValues);
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/// LowerCallTo - This hook lowers an abstract call to a function into an
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/// LowerCallTo - This hook lowers an abstract call to a function into an
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/// actual call. This returns a pair of operands. The first element is the
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/// actual call. This returns a pair of operands. The first element is the
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@ -474,7 +474,7 @@ class SelectionDAGLowering {
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/// them up and then emit token factor nodes when possible. This allows us to
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/// them up and then emit token factor nodes when possible. This allows us to
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/// get simple disambiguation between loads without worrying about alias
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/// get simple disambiguation between loads without worrying about alias
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/// analysis.
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/// analysis.
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std::vector<SDOperand> PendingLoads;
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SmallVector<SDOperand, 8> PendingLoads;
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/// PendingExports - CopyToReg nodes that copy values to virtual registers
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/// PendingExports - CopyToReg nodes that copy values to virtual registers
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/// for export to other blocks need to be emitted before any terminator
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/// for export to other blocks need to be emitted before any terminator
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@ -4612,16 +4612,16 @@ void SelectionDAGLowering::visitVACopy(CallInst &I) {
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/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
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/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
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/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
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/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
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/// integrated into SDISel.
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/// integrated into SDISel.
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std::vector<SDOperand>
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void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
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TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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SmallVectorImpl<SDOperand> &ArgValues) {
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// Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
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// Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
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std::vector<SDOperand> Ops;
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SmallVector<SDOperand, 3+16> Ops;
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Ops.push_back(DAG.getRoot());
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Ops.push_back(DAG.getRoot());
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Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
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Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
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Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
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Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
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// Add one result value for each formal argument.
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// Add one result value for each formal argument.
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std::vector<MVT> RetVals;
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SmallVector<MVT, 16> RetVals;
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unsigned j = 1;
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unsigned j = 1;
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
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I != E; ++I, ++j) {
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I != E; ++I, ++j) {
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@ -4699,7 +4699,6 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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DAG.setRoot(SDOperand(Result, NumArgRegs));
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DAG.setRoot(SDOperand(Result, NumArgRegs));
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// Set up the return result vector.
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// Set up the return result vector.
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Ops.clear();
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unsigned i = 0;
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unsigned i = 0;
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unsigned Idx = 1;
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unsigned Idx = 1;
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
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@ -4722,12 +4721,11 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
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else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
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AssertOp = ISD::AssertZext;
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AssertOp = ISD::AssertZext;
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Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
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ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
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AssertOp));
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AssertOp));
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}
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}
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}
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}
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assert(i == NumArgRegs && "Argument register count mismatch!");
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assert(i == NumArgRegs && "Argument register count mismatch!");
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return Ops;
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}
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}
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@ -4951,7 +4949,8 @@ LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) {
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Function &F = *LLVMBB->getParent();
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Function &F = *LLVMBB->getParent();
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FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
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FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
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SDOperand OldRoot = SDL.DAG.getRoot();
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SDOperand OldRoot = SDL.DAG.getRoot();
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std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
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SmallVector<SDOperand, 16> Args;
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TLI.LowerArguments(F, SDL.DAG, Args);
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unsigned a = 0;
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unsigned a = 0;
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for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
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for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
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@ -143,9 +143,8 @@ MVT IA64TargetLowering::getSetCCResultType(const SDOperand &) const {
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return MVT::i1;
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return MVT::i1;
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}
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}
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std::vector<SDOperand>
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void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
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IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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SmallVectorImpl<SDOperand> &ArgValues) {
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std::vector<SDOperand> ArgValues;
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//
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//
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// add beautiful description of IA64 stack frame format
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// add beautiful description of IA64 stack frame format
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// here (from intel 24535803.pdf most likely)
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// here (from intel 24535803.pdf most likely)
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@ -300,8 +299,6 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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MF.getRegInfo().addLiveOut(IA64::F8);
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MF.getRegInfo().addLiveOut(IA64::F8);
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break;
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break;
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}
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}
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return ArgValues;
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}
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}
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std::pair<SDOperand, SDOperand>
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std::pair<SDOperand, SDOperand>
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@ -53,8 +53,8 @@ namespace llvm {
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/// LowerArguments - This hook must be implemented to indicate how we should
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/// LowerArguments - This hook must be implemented to indicate how we should
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/// lower the arguments for the specified function, into the specified DAG.
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/// lower the arguments for the specified function, into the specified DAG.
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virtual std::vector<SDOperand>
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virtual void LowerArguments(Function &F, SelectionDAG &DAG,
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LowerArguments(Function &F, SelectionDAG &DAG);
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SmallVectorImpl<SDOperand> &ArgValues);
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/// LowerCallTo - This hook lowers an abstract call to a function into an
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/// LowerCallTo - This hook lowers an abstract call to a function into an
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/// actual call.
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/// actual call.
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@ -74,11 +74,11 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
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/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
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/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
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/// either one or two GPRs, including FP values. TODO: we should pass FP values
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/// either one or two GPRs, including FP values. TODO: we should pass FP values
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/// in FP registers for fastcc functions.
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/// in FP registers for fastcc functions.
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std::vector<SDOperand>
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void
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SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
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SmallVectorImpl<SDOperand> &ArgValues) {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFunction &MF = DAG.getMachineFunction();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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std::vector<SDOperand> ArgValues;
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static const unsigned ArgRegs[] = {
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static const unsigned ArgRegs[] = {
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SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
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SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
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@ -221,8 +221,6 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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if (!OutChains.empty())
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if (!OutChains.empty())
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DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
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DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
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&OutChains[0], OutChains.size()));
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&OutChains[0], OutChains.size()));
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return ArgValues;
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}
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}
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static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
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static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
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@ -57,8 +57,8 @@ namespace llvm {
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const SelectionDAG &DAG,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const;
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unsigned Depth = 0) const;
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virtual std::vector<SDOperand>
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virtual void LowerArguments(Function &F, SelectionDAG &DAG,
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LowerArguments(Function &F, SelectionDAG &DAG);
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SmallVectorImpl<SDOperand> &ArgValues);
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virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
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virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB);
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MachineBasicBlock *MBB);
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