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ARM optional destination operand variants for VEXT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146114 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -5491,3 +5491,20 @@ def : NEONInstAlias<"vclt${p}.u32 $Qd, $Qn, $Qm",
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(VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
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def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm",
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(VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
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// Two-operand variants for VEXT
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def : NEONInstAlias<"vext${p}.8 $Vdn, $Vm, $imm",
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(VEXTd8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_7:$imm, pred:$p)>;
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def : NEONInstAlias<"vext${p}.16 $Vdn, $Vm, $imm",
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(VEXTd16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_3:$imm, pred:$p)>;
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def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm",
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(VEXTd32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_1:$imm, pred:$p)>;
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def : NEONInstAlias<"vext${p}.8 $Vdn, $Vm, $imm",
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(VEXTq8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_15:$imm, pred:$p)>;
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def : NEONInstAlias<"vext${p}.16 $Vdn, $Vm, $imm",
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(VEXTq16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_7:$imm, pred:$p)>;
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def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm",
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(VEXTq32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_3:$imm, pred:$p)>;
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def : NEONInstAlias<"vext${p}.64 $Vdn, $Vm, $imm",
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(VEXTq64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_1:$imm, pred:$p)>;
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@ -7,6 +7,14 @@
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vext.16 d16, d17, d16, #3
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vext.32 q8, q9, q8, #3
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vext.8 d17, d16, #3
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vext.8 d7, d11, #5
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vext.8 q3, q8, #3
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vext.8 q9, q4, #7
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vext.16 d1, d26, #3
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vext.32 q5, q8, #3
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@ CHECK: vext.8 d16, d17, d16, #3 @ encoding: [0xa0,0x03,0xf1,0xf2]
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@ CHECK: vext.8 d16, d17, d16, #5 @ encoding: [0xa0,0x05,0xf1,0xf2]
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@ CHECK: vext.8 q8, q9, q8, #3 @ encoding: [0xe0,0x03,0xf2,0xf2]
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@ -14,6 +22,13 @@
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@ CHECK: vext.16 d16, d17, d16, #3 @ encoding: [0xa0,0x06,0xf1,0xf2]
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@ CHECK: vext.32 q8, q9, q8, #3 @ encoding: [0xe0,0x0c,0xf2,0xf2]
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@ CHECK: vext.8 d17, d17, d16, #3 @ encoding: [0xa0,0x13,0xf1,0xf2]
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@ CHECK: vext.8 d7, d7, d11, #5 @ encoding: [0x0b,0x75,0xb7,0xf2]
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@ CHECK: vext.8 q3, q3, q8, #3 @ encoding: [0x60,0x63,0xb6,0xf2]
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@ CHECK: vext.8 q9, q9, q4, #7 @ encoding: [0xc8,0x27,0xf2,0xf2]
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@ CHECK: vext.16 d1, d1, d26, #3 @ encoding: [0x2a,0x16,0xb1,0xf2]
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@ CHECK: vext.32 q5, q5, q8, #3 @ encoding: [0x60,0xac,0xba,0xf2]
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vtrn.8 d17, d16
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vtrn.16 d17, d16
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