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[Hexagon] Adding post-increment unsigned byte loads.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224867 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2014-12-26 19:12:11 +00:00
parent 3c52b7b9f2
commit a46bee194d
4 changed files with 35 additions and 24 deletions
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2
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
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@ -610,7 +610,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
Opcode = zextval ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io; Opcode = zextval ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io;
} else if (LoadedVT == MVT::i8) { } else if (LoadedVT == MVT::i8) {
if (TII->isValidAutoIncImm(LoadedVT, Val)) if (TII->isValidAutoIncImm(LoadedVT, Val))
Opcode = zextval ? Hexagon::POST_LDriub : Hexagon::L2_loadrb_pi; Opcode = zextval ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrb_pi;
else else
Opcode = zextval ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io; Opcode = zextval ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io;
} else } else

6
lib/Target/Hexagon/HexagonInstrInfo.cpp
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@ -695,7 +695,7 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
return isShiftedInt<4,1>(MI->getOperand(3).getImm()); return isShiftedInt<4,1>(MI->getOperand(3).getImm());
case Hexagon::L2_loadrb_pi: case Hexagon::L2_loadrb_pi:
case Hexagon::POST_LDriub: case Hexagon::L2_loadrub_pi:
return isInt<4>(MI->getOperand(3).getImm()); return isInt<4>(MI->getOperand(3).getImm());
case Hexagon::STrib_imm_V4: case Hexagon::STrib_imm_V4:
@ -1367,8 +1367,8 @@ isConditionalLoad (const MachineInstr* MI) const {
case Hexagon::L2_ploadrbf_pi : case Hexagon::L2_ploadrbf_pi :
case Hexagon::POST_LDriuh_cPt : case Hexagon::POST_LDriuh_cPt :
case Hexagon::POST_LDriuh_cNotPt : case Hexagon::POST_LDriuh_cNotPt :
case Hexagon::POST_LDriub_cPt : case Hexagon::L2_ploadrubt_pi :
case Hexagon::POST_LDriub_cNotPt : case Hexagon::L2_ploadrubf_pi :
return QRI.Subtarget.hasV4TOps(); return QRI.Subtarget.hasV4TOps();
case Hexagon::LDrid_indexed_shl_cPt_V4 : case Hexagon::LDrid_indexed_shl_cPt_V4 :
case Hexagon::LDrid_indexed_shl_cNotPt_V4 : case Hexagon::LDrid_indexed_shl_cNotPt_V4 :

3
lib/Target/Hexagon/HexagonInstrInfo.td
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@ -1698,6 +1698,7 @@ multiclass LD_PostInc <string mnemonic, string BaseOp, RegisterClass RC,
// post increment byte loads with immediate offset // post increment byte loads with immediate offset
let accessSize = ByteAccess, isCodeGenOnly = 0 in { let accessSize = ByteAccess, isCodeGenOnly = 0 in {
defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>; defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>;
defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>;
} }
multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp, multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
@ -1740,8 +1741,6 @@ multiclass LD_PostInc2<string mnemonic, string BaseOp, RegisterClass RC,
} }
let hasCtrlDep = 1, hasSideEffects = 0, addrMode = PostInc in { let hasCtrlDep = 1, hasSideEffects = 0, addrMode = PostInc in {
defm POST_LDriub : LD_PostInc2<"memub", "LDriub", IntRegs, s4_0Imm>,
PredNewRel;
defm POST_LDrih : LD_PostInc2<"memh", "LDrih", IntRegs, s4_1Imm>, defm POST_LDrih : LD_PostInc2<"memh", "LDrih", IntRegs, s4_1Imm>,
PredNewRel; PredNewRel;
defm POST_LDriuh : LD_PostInc2<"memuh", "LDriuh", IntRegs, s4_1Imm>, defm POST_LDriuh : LD_PostInc2<"memuh", "LDriuh", IntRegs, s4_1Imm>,

48
test/MC/Disassembler/Hexagon/ld.txt
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@ -13,6 +13,8 @@
0xf1 0xc3 0x15 0x91 0xf1 0xc3 0x15 0x91
# CHECK: r17 = memb(r21 + #31) # CHECK: r17 = memb(r21 + #31)
0xb1 0xc0 0x15 0x9b
# CHECK: r17 = memb(r21++#5)
0x91 0xdd 0x15 0x41 0x91 0xdd 0x15 0x41
# CHECK: if (p3) r17 = memb(r21 + #44) # CHECK: if (p3) r17 = memb(r21 + #44)
0x03 0x40 0x45 0x85 0x91 0xdd 0x15 0x43 0x03 0x40 0x45 0x85 0x91 0xdd 0x15 0x43
@ -23,24 +25,6 @@
0x03 0x40 0x45 0x85 0x91 0xdd 0x15 0x47 0x03 0x40 0x45 0x85 0x91 0xdd 0x15 0x47
# CHECK: p3 = r5 # CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = memb(r21 + #44) # CHECK-NEXT: if (!p3.new) r17 = memb(r21 + #44)
0xf1 0xc3 0x55 0x91
# CHECK: r17 = memh(r21 + #62)
0xf1 0xc3 0x35 0x91
# CHECK: r17 = memub(r21 + #31)
0xb1 0xc0 0x15 0x9b
# CHECK: r17 = memb(r21++#5)
0xf1 0xdb 0x35 0x41
# CHECK: if (p3) r17 = memub(r21 + #31)
0x03 0x40 0x45 0x85 0xf1 0xdb 0x35 0x43
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) r17 = memub(r21 + #31)
0xf1 0xdb 0x35 0x45
# CHECK: if (!p3) r17 = memub(r21 + #31)
0x03 0x40 0x45 0x85 0xf1 0xdb 0x35 0x47
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = memub(r21 + #31)
0xb1 0xe6 0x15 0x9b 0xb1 0xe6 0x15 0x9b
# CHECK: if (p3) r17 = memb(r21++#5) # CHECK: if (p3) r17 = memb(r21++#5)
0xb1 0xee 0x15 0x9b 0xb1 0xee 0x15 0x9b
@ -52,6 +36,34 @@
# CHECK: p3 = r5 # CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = memb(r21++#5) # CHECK-NEXT: if (!p3.new) r17 = memb(r21++#5)
0xf1 0xc3 0x55 0x91
# CHECK: r17 = memh(r21 + #62)
0xf1 0xc3 0x35 0x91
# CHECK: r17 = memub(r21 + #31)
0xb1 0xc0 0x35 0x9b
# CHECK: r17 = memub(r21++#5)
0xf1 0xdb 0x35 0x41
# CHECK: if (p3) r17 = memub(r21 + #31)
0x03 0x40 0x45 0x85 0xf1 0xdb 0x35 0x43
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) r17 = memub(r21 + #31)
0xf1 0xdb 0x35 0x45
# CHECK: if (!p3) r17 = memub(r21 + #31)
0x03 0x40 0x45 0x85 0xf1 0xdb 0x35 0x47
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = memub(r21 + #31)
0xb1 0xe6 0x35 0x9b
# CHECK: if (p3) r17 = memub(r21++#5)
0xb1 0xee 0x35 0x9b
# CHECK: if (!p3) r17 = memub(r21++#5)
0x03 0x40 0x45 0x85 0xb1 0xf6 0x35 0x9b
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) r17 = memub(r21++#5)
0x03 0x40 0x45 0x85 0xb1 0xfe 0x35 0x9b
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = memub(r21++#5)
0xb1 0xc2 0x75 0x91 0xb1 0xc2 0x75 0x91
# CHECK: r17 = memuh(r21 + #42) # CHECK: r17 = memuh(r21 + #42)
0xb1 0xda 0x75 0x41 0xb1 0xda 0x75 0x41