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remove support for llvm.isunordered
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32992 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -843,22 +843,6 @@ void SelectionDAGLowering::FindMergedConditions(Value *Cond,
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!InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
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const BasicBlock *BB = CurBB->getBasicBlock();
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if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(Cond))
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if ((II->getIntrinsicID() == Intrinsic::isunordered_f32 ||
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II->getIntrinsicID() == Intrinsic::isunordered_f64) &&
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// The operands of the setcc have to be in this block. We don't know
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// how to export them from some other block. If this is the first
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// block of the sequence, no exporting is needed.
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(CurBB == CurMBB ||
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(isExportableFromCurrentBlock(II->getOperand(1), BB) &&
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isExportableFromCurrentBlock(II->getOperand(2), BB)))) {
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SelectionDAGISel::CaseBlock CB(ISD::SETUO, II->getOperand(1),
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II->getOperand(2), TBB, FBB, CurBB);
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SwitchCases.push_back(CB);
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return;
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}
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// If the leaf of the tree is a comparison, merge the condition into
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// the caseblock.
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if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
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@ -2038,12 +2022,6 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
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return 0;
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}
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case Intrinsic::isunordered_f32:
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case Intrinsic::isunordered_f64:
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setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
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getValue(I.getOperand(2)), ISD::SETUO));
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return 0;
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case Intrinsic::sqrt_f32:
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case Intrinsic::sqrt_f64:
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setValue(&I, DAG.getNode(ISD::FSQRT,
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