6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-17 21:29:20 +00:00
Code Issues Projects Releases Wiki Activity

remove support for llvm.isunordered

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32992 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-01-07 08:37:22 +00:00
parent 257cbf7a8d
commit a4810b52d0
1 changed files with 0 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -843,22 +843,6 @@ void SelectionDAGLowering::FindMergedConditions(Value *Cond,
!InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
const BasicBlock *BB = CurBB->getBasicBlock();
if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(Cond))
if ((II->getIntrinsicID() == Intrinsic::isunordered_f32 ||
II->getIntrinsicID() == Intrinsic::isunordered_f64) &&
// The operands of the setcc have to be in this block. We don't know
// how to export them from some other block. If this is the first
// block of the sequence, no exporting is needed.
(CurBB == CurMBB ||
(isExportableFromCurrentBlock(II->getOperand(1), BB) &&
isExportableFromCurrentBlock(II->getOperand(2), BB)))) {
SelectionDAGISel::CaseBlock CB(ISD::SETUO, II->getOperand(1),
II->getOperand(2), TBB, FBB, CurBB);
SwitchCases.push_back(CB);
return;
}
// If the leaf of the tree is a comparison, merge the condition into
// the caseblock.
if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
@ -2038,12 +2022,6 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
return 0;
}
case Intrinsic::isunordered_f32:
case Intrinsic::isunordered_f64:
setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
getValue(I.getOperand(2)), ISD::SETUO));
return 0;
case Intrinsic::sqrt_f32:
case Intrinsic::sqrt_f64:
setValue(&I, DAG.getNode(ISD::FSQRT,