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AMDGPU/SI: Simplify moveSMRDToVALU()
Summary: Replace the switch on instruction opcode with a switch on register size. This way we don't need to update the switch statement when we add new SMRD variants. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11601 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243652 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2056,13 +2056,13 @@ void SIInstrInfo::splitSMRD(MachineInstr *MI,
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void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
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MachineBasicBlock *MBB = MI->getParent();
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switch (MI->getOpcode()) {
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case AMDGPU::S_LOAD_DWORD_IMM:
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case AMDGPU::S_LOAD_DWORD_SGPR:
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case AMDGPU::S_LOAD_DWORDX2_IMM:
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case AMDGPU::S_LOAD_DWORDX2_SGPR:
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case AMDGPU::S_LOAD_DWORDX4_IMM:
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case AMDGPU::S_LOAD_DWORDX4_SGPR: {
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int DstIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
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assert(DstIdx != -1);
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unsigned DstRCID = get(MI->getOpcode()).OpInfo[DstIdx].RegClass;
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switch(RI.getRegClass(DstRCID)->getSize()) {
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case 4:
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case 8:
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case 16: {
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unsigned NewOpcode = getVALUOp(*MI);
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unsigned RegOffset;
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unsigned ImmOffset;
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@ -2134,8 +2134,7 @@ void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) con
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MRI.replaceRegWith(DstReg, NewDstReg);
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break;
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}
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case AMDGPU::S_LOAD_DWORDX8_IMM:
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case AMDGPU::S_LOAD_DWORDX8_SGPR: {
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case 32: {
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MachineInstr *Lo, *Hi;
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splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
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AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
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@ -2145,8 +2144,7 @@ void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) con
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break;
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}
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case AMDGPU::S_LOAD_DWORDX16_IMM:
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case AMDGPU::S_LOAD_DWORDX16_SGPR: {
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case 64: {
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MachineInstr *Lo, *Hi;
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splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
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AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
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