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move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helper

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functions in ARMBaseInfo.h so it can be used in the MC library as well.
For anything bigger than this, we may want a means to have a small support
library for shared helper functions like this. Cross that bridge when we
come to it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114016 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-09-15 20:26:25 +00:00
parent 39e30124e5
commit a4c3c8f28d
7 changed files with 82 additions and 89 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -344,7 +344,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
<< getRegisterName(DRegLo) << ", " << getRegisterName(DRegHi) << getRegisterName(DRegLo) << ", " << getRegisterName(DRegHi)
<< '}'; << '}';
} else if (Modifier && strcmp(Modifier, "lane") == 0) { } else if (Modifier && strcmp(Modifier, "lane") == 0) {
unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg); unsigned RegNum = getARMRegisterNumbering(Reg);
unsigned DReg = unsigned DReg =
TM.getRegisterInfo()->getMatchingSuperReg(Reg, TM.getRegisterInfo()->getMatchingSuperReg(Reg,
RegNum & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass); RegNum & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass);

68
lib/Target/ARM/ARMBaseInfo.h
View File

@ -19,6 +19,18 @@
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
// Note that the following auto-generated files only defined enum types, and
// so are safe to include here.
// Defines symbolic names for ARM registers. This defines a mapping from
// register name to register number.
//
#include "ARMGenRegisterNames.inc"
// Defines symbolic names for the ARM instructions.
//
#include "ARMGenInstrNames.inc"
namespace llvm { namespace llvm {
// Enums corresponding to ARM condition codes // Enums corresponding to ARM condition codes
@ -111,18 +123,50 @@ namespace ARM_MB {
} }
} }
} // namespace ARM_MB } // namespace ARM_MB
/// getARMRegisterNumbering - Given the enum value for some register, e.g.
/// ARM::LR, return the number that it corresponds to (e.g. 14).
inline static unsigned getARMRegisterNumbering(unsigned Reg) {
using namespace ARM;
switch (Reg) {
default:
llvm_unreachable("Unknown ARM register!");
case R0: case S0: case D0: case Q0: return 0;
case R1: case S1: case D1: case Q1: return 1;
case R2: case S2: case D2: case Q2: return 2;
case R3: case S3: case D3: case Q3: return 3;
case R4: case S4: case D4: case Q4: return 4;
case R5: case S5: case D5: case Q5: return 5;
case R6: case S6: case D6: case Q6: return 6;
case R7: case S7: case D7: case Q7: return 7;
case R8: case S8: case D8: case Q8: return 8;
case R9: case S9: case D9: case Q9: return 9;
case R10: case S10: case D10: case Q10: return 10;
case R11: case S11: case D11: case Q11: return 11;
case R12: case S12: case D12: case Q12: return 12;
case SP: case S13: case D13: case Q13: return 13;
case LR: case S14: case D14: case Q14: return 14;
case PC: case S15: case D15: case Q15: return 15;
case S16: case D16: return 16;
case S17: case D17: return 17;
case S18: case D18: return 18;
case S19: case D19: return 19;
case S20: case D20: return 20;
case S21: case D21: return 21;
case S22: case D22: return 22;
case S23: case D23: return 23;
case S24: case D24: return 24;
case S25: case D25: return 25;
case S26: case D26: return 26;
case S27: case D27: return 27;
case S28: case D28: return 28;
case S29: case D29: return 29;
case S30: case D30: return 30;
case S31: case D31: return 31;
}
}
} // end namespace llvm; } // end namespace llvm;
// Note that the following auto-generated files only defined enum types, and
// so are safe to include here.
// Defines symbolic names for ARM registers. This defines a mapping from
// register name to register number.
//
#include "ARMGenRegisterNames.inc"
// Defines symbolic names for the ARM instructions.
//
#include "ARMGenInstrNames.inc"
#endif #endif

40
lib/Target/ARM/ARMBaseRegisterInfo.cpp
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@ -54,46 +54,6 @@ static cl::opt<bool>
EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true), EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
cl::desc("Enable use of a base pointer for complex stack frames")); cl::desc("Enable use of a base pointer for complex stack frames"));
unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned Reg) {
using namespace ARM;
switch (Reg) {
default:
llvm_unreachable("Unknown ARM register!");
case R0: case S0: case D0: case Q0: return 0;
case R1: case S1: case D1: case Q1: return 1;
case R2: case S2: case D2: case Q2: return 2;
case R3: case S3: case D3: case Q3: return 3;
case R4: case S4: case D4: case Q4: return 4;
case R5: case S5: case D5: case Q5: return 5;
case R6: case S6: case D6: case Q6: return 6;
case R7: case S7: case D7: case Q7: return 7;
case R8: case S8: case D8: case Q8: return 8;
case R9: case S9: case D9: case Q9: return 9;
case R10: case S10: case D10: case Q10: return 10;
case R11: case S11: case D11: case Q11: return 11;
case R12: case S12: case D12: case Q12: return 12;
case SP: case S13: case D13: case Q13: return 13;
case LR: case S14: case D14: case Q14: return 14;
case PC: case S15: case D15: case Q15: return 15;
case S16: case D16: return 16;
case S17: case D17: return 17;
case S18: case D18: return 18;
case S19: case D19: return 19;
case S20: case D20: return 20;
case S21: case D21: return 21;
case S22: case D22: return 22;
case S23: case D23: return 23;
case S24: case D24: return 24;
case S25: case D25: return 25;
case S26: case D26: return 26;
case S27: case D27: return 27;
case S28: case D28: return 28;
case S29: case D29: return 29;
case S30: case D30: return 30;
case S31: case D31: return 31;
}
}
ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
const ARMSubtarget &sti) const ARMSubtarget &sti)

4
lib/Target/ARM/ARMBaseRegisterInfo.h
View File

@ -65,10 +65,6 @@ protected:
unsigned getOpcode(int Op) const; unsigned getOpcode(int Op) const;
public: public:
/// getRegisterNumbering - Given the enum value for some register, e.g.
/// ARM::LR, return the number that it corresponds to (e.g. 14).
static unsigned getRegisterNumbering(unsigned Reg);
/// Code Generation virtual methods... /// Code Generation virtual methods...
const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const; const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;

51
lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -264,7 +264,7 @@ unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
const MachineOperand &MO) { const MachineOperand &MO) {
if (MO.isReg()) if (MO.isReg())
return ARMRegisterInfo::getRegisterNumbering(MO.getReg()); return getARMRegisterNumbering(MO.getReg());
else if (MO.isImm()) else if (MO.isImm())
return static_cast<unsigned>(MO.getImm()); return static_cast<unsigned>(MO.getImm());
else if (MO.isGlobal()) else if (MO.isGlobal())
@ -596,7 +596,7 @@ void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
// Encode Rn which is PC. // Encode Rn which is PC.
Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift; Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
// Encode the displacement. // Encode the displacement.
Binary |= 1 << ARMII::I_BitShift; Binary |= 1 << ARMII::I_BitShift;
@ -785,8 +785,7 @@ unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
if (Rs) { if (Rs) {
// Encode Rs bit[11:8]. // Encode Rs bit[11:8].
assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
return Binary | return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
(ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
} }
// Encode shift_imm bit[11:7]. // Encode shift_imm bit[11:7].
@ -837,8 +836,7 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
else if (ImplicitRd) else if (ImplicitRd)
// Special handling for implicit use (e.g. PC). // Special handling for implicit use (e.g. PC).
Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd) Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
<< ARMII::RegRdShift);
if (TID.Opcode == ARM::MOVi16) { if (TID.Opcode == ARM::MOVi16) {
// Get immediate from MI. // Get immediate from MI.
@ -888,8 +886,7 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
if (!isUnary) { if (!isUnary) {
if (ImplicitRn) if (ImplicitRn)
// Special handling for implicit use (e.g. PC). // Special handling for implicit use (e.g. PC).
Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn) Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
<< ARMII::RegRnShift);
else { else {
Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift; Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
++OpIdx; ++OpIdx;
@ -906,7 +903,7 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
if (MO.isReg()) { if (MO.isReg()) {
// Encode register Rm. // Encode register Rm.
emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg())); emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
return; return;
} }
@ -942,16 +939,14 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
// Set first operand // Set first operand
if (ImplicitRd) if (ImplicitRd)
// Special handling for implicit use (e.g. PC). // Special handling for implicit use (e.g. PC).
Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd) Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
<< ARMII::RegRdShift);
else else
Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
// Set second operand // Set second operand
if (ImplicitRn) if (ImplicitRn)
// Special handling for implicit use (e.g. PC). // Special handling for implicit use (e.g. PC).
Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn) Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
<< ARMII::RegRnShift);
else else
Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
@ -978,7 +973,7 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
Binary |= 1 << ARMII::I_BitShift; Binary |= 1 << ARMII::I_BitShift;
assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
// Set bit[3:0] to the corresponding Rm register // Set bit[3:0] to the corresponding Rm register
Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg()); Binary |= getARMRegisterNumbering(MO2.getReg());
// If this instr is in scaled register offset/index instruction, set // If this instr is in scaled register offset/index instruction, set
// shift_immed(bit[11:7]) and shift(bit[6:5]) fields. // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
@ -1022,8 +1017,7 @@ void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
// Set second operand // Set second operand
if (ImplicitRn) if (ImplicitRn)
// Special handling for implicit use (e.g. PC). // Special handling for implicit use (e.g. PC).
Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn) Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
<< ARMII::RegRnShift);
else else
Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
@ -1042,7 +1036,7 @@ void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
// If this instr is in register offset/index encoding, set bit[3:0] // If this instr is in register offset/index encoding, set bit[3:0]
// to the corresponding Rm register. // to the corresponding Rm register.
if (MO2.getReg()) { if (MO2.getReg()) {
Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg()); Binary |= getARMRegisterNumbering(MO2.getReg());
emitWordLE(Binary); emitWordLE(Binary);
return; return;
} }
@ -1108,7 +1102,7 @@ void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
const MachineOperand &MO = MI.getOperand(i); const MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg() || MO.isImplicit()) if (!MO.isReg() || MO.isImplicit())
break; break;
unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg()); unsigned RegNum = getARMRegisterNumbering(MO.getReg());
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
RegNum < 16); RegNum < 16);
Binary |= 0x1 << RegNum; Binary |= 0x1 << RegNum;
@ -1345,7 +1339,7 @@ void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR) if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
// The return register is LR. // The return register is LR.
Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR); Binary |= getARMRegisterNumbering(ARM::LR);
else else
// otherwise, set the return register // otherwise, set the return register
Binary |= getMachineOpValue(MI, 0); Binary |= getMachineOpValue(MI, 0);
@ -1357,7 +1351,7 @@ static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
unsigned RegD = MI.getOperand(OpIdx).getReg(); unsigned RegD = MI.getOperand(OpIdx).getReg();
unsigned Binary = 0; unsigned Binary = 0;
bool isSPVFP = ARM::SPRRegisterClass->contains(RegD); bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
RegD = ARMRegisterInfo::getRegisterNumbering(RegD); RegD = getARMRegisterNumbering(RegD);
if (!isSPVFP) if (!isSPVFP)
Binary |= RegD << ARMII::RegRdShift; Binary |= RegD << ARMII::RegRdShift;
else { else {
@ -1371,7 +1365,7 @@ static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
unsigned RegN = MI.getOperand(OpIdx).getReg(); unsigned RegN = MI.getOperand(OpIdx).getReg();
unsigned Binary = 0; unsigned Binary = 0;
bool isSPVFP = ARM::SPRRegisterClass->contains(RegN); bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
RegN = ARMRegisterInfo::getRegisterNumbering(RegN); RegN = getARMRegisterNumbering(RegN);
if (!isSPVFP) if (!isSPVFP)
Binary |= RegN << ARMII::RegRnShift; Binary |= RegN << ARMII::RegRnShift;
else { else {
@ -1385,7 +1379,7 @@ static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
unsigned RegM = MI.getOperand(OpIdx).getReg(); unsigned RegM = MI.getOperand(OpIdx).getReg();
unsigned Binary = 0; unsigned Binary = 0;
bool isSPVFP = ARM::SPRRegisterClass->contains(RegM); bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
RegM = ARMRegisterInfo::getRegisterNumbering(RegM); RegM = getARMRegisterNumbering(RegM);
if (!isSPVFP) if (!isSPVFP)
Binary |= RegM; Binary |= RegM;
else { else {
@ -1592,8 +1586,7 @@ void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
case ARM::VMSR: { case ARM::VMSR: {
const MachineOperand &MO0 = MI.getOperand(0); const MachineOperand &MO0 = MI.getOperand(0);
// Encode Rt. // Encode Rt.
Binary |= ARMRegisterInfo::getRegisterNumbering(MO0.getReg()) Binary |= getARMRegisterNumbering(MO0.getReg()) << ARMII::RegRdShift;
<< ARMII::RegRdShift;
break; break;
} }
@ -1628,7 +1621,7 @@ void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) { static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
unsigned RegD = MI.getOperand(OpIdx).getReg(); unsigned RegD = MI.getOperand(OpIdx).getReg();
unsigned Binary = 0; unsigned Binary = 0;
RegD = ARMRegisterInfo::getRegisterNumbering(RegD); RegD = getARMRegisterNumbering(RegD);
Binary |= (RegD & 0xf) << ARMII::RegRdShift; Binary |= (RegD & 0xf) << ARMII::RegRdShift;
Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift; Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
return Binary; return Binary;
@ -1637,7 +1630,7 @@ static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) { static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
unsigned RegN = MI.getOperand(OpIdx).getReg(); unsigned RegN = MI.getOperand(OpIdx).getReg();
unsigned Binary = 0; unsigned Binary = 0;
RegN = ARMRegisterInfo::getRegisterNumbering(RegN); RegN = getARMRegisterNumbering(RegN);
Binary |= (RegN & 0xf) << ARMII::RegRnShift; Binary |= (RegN & 0xf) << ARMII::RegRnShift;
Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift; Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
return Binary; return Binary;
@ -1646,7 +1639,7 @@ static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) { static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
unsigned RegM = MI.getOperand(OpIdx).getReg(); unsigned RegM = MI.getOperand(OpIdx).getReg();
unsigned Binary = 0; unsigned Binary = 0;
RegM = ARMRegisterInfo::getRegisterNumbering(RegM); RegM = getARMRegisterNumbering(RegM);
Binary |= (RegM & 0xf); Binary |= (RegM & 0xf);
Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift; Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
return Binary; return Binary;
@ -1680,7 +1673,7 @@ void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
unsigned RegT = MI.getOperand(RegTOpIdx).getReg(); unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
RegT = ARMRegisterInfo::getRegisterNumbering(RegT); RegT = getARMRegisterNumbering(RegT);
Binary |= (RegT << ARMII::RegRdShift); Binary |= (RegT << ARMII::RegRdShift);
Binary |= encodeNEONRn(MI, RegNOpIdx); Binary |= encodeNEONRn(MI, RegNOpIdx);
@ -1709,7 +1702,7 @@ void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
unsigned RegT = MI.getOperand(1).getReg(); unsigned RegT = MI.getOperand(1).getReg();
RegT = ARMRegisterInfo::getRegisterNumbering(RegT); RegT = getARMRegisterNumbering(RegT);
Binary |= (RegT << ARMII::RegRdShift); Binary |= (RegT << ARMII::RegRdShift);
Binary |= encodeNEONRn(MI, 0); Binary |= encodeNEONRn(MI, 0);
emitWordLE(Binary); emitWordLE(Binary);

2
lib/Target/ARM/ARMJITInfo.cpp
View File

@ -290,7 +290,7 @@ void ARMJITInfo::relocate(void *Function, MachineRelocation *MR,
*((intptr_t*)RelocPos) |= ResultPtr; *((intptr_t*)RelocPos) |= ResultPtr;
// Set register Rn to PC. // Set register Rn to PC.
*((intptr_t*)RelocPos) |= *((intptr_t*)RelocPos) |=
ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift; getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
break; break;
} }
case ARM::reloc_arm_pic_jt: case ARM::reloc_arm_pic_jt:

4
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -349,7 +349,7 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
const MachineOperand &PMO = Loc->getOperand(0); const MachineOperand &PMO = Loc->getOperand(0);
unsigned PReg = PMO.getReg(); unsigned PReg = PMO.getReg();
unsigned PRegNum = PMO.isUndef() ? UINT_MAX unsigned PRegNum = PMO.isUndef() ? UINT_MAX
: ARMRegisterInfo::getRegisterNumbering(PReg); : getARMRegisterNumbering(PReg);
unsigned Count = 1; unsigned Count = 1;
for (unsigned i = SIndex+1, e = MemOps.size(); i != e; ++i) { for (unsigned i = SIndex+1, e = MemOps.size(); i != e; ++i) {
@ -357,7 +357,7 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
const MachineOperand &MO = MemOps[i].MBBI->getOperand(0); const MachineOperand &MO = MemOps[i].MBBI->getOperand(0);
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
unsigned RegNum = MO.isUndef() ? UINT_MAX unsigned RegNum = MO.isUndef() ? UINT_MAX
: ARMRegisterInfo::getRegisterNumbering(Reg); : getARMRegisterNumbering(Reg);
// Register numbers must be in ascending order. For VFP, the registers // Register numbers must be in ascending order. For VFP, the registers
// must also be consecutive and there is a limit of 16 double-word // must also be consecutive and there is a limit of 16 double-word
// registers per instruction. // registers per instruction.