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Temporarily revert r220777 to sort out build bot breakage.
"[x86] Simplify vector selection if condition value type matches vselect value type and true value is all ones or false value is all zeros." git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221028 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -22468,22 +22468,22 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
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return DAG.getNode(Opc, DL, VT, LHS, RHS);
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}
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// Simplify vector selection if condition value type matches vselect
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// operand type
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if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
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// Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
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if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
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// Check if SETCC has already been promoted
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TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
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// Check that condition value type matches vselect operand type
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CondVT == VT) {
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assert(Cond.getValueType().isVector() &&
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"vector select expects a vector selector!");
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bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
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bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
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// Try invert the condition if true value is not all 1s and false value
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// is not all 0s.
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if (!TValIsAllOnes && !FValIsAllZeros &&
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// Check if the selector will be produced by CMPP*/PCMP*
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Cond.getOpcode() == ISD::SETCC &&
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// Check if SETCC has already been promoted
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TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
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if (!TValIsAllOnes && !FValIsAllZeros) {
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// Try invert the condition if true value is not all 1s and false value
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// is not all 0s.
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bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
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bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
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@ -48,47 +48,3 @@ define <16 x double> @select04(<16 x double> %a, <16 x double> %b) {
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%sel = select <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x double> %a, <16 x double> %b
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ret <16 x double> %sel
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}
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; CHECK-LABEL: select05
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; CHECK: kmovw %esi, %k0
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: korw %k1, %k0, %k0
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; CHECK-NEXT: kmovw %k0, %eax
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define i8 @select05(i8 %a.0, i8 %m) {
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%mask = bitcast i8 %m to <8 x i1>
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%a = bitcast i8 %a.0 to <8 x i1>
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%r = select <8 x i1> %mask, <8 x i1> <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>, <8 x i1> %a
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%res = bitcast <8 x i1> %r to i8
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ret i8 %res;
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}
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; CHECK-LABEL: select06
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; CHECK: kmovw %esi, %k0
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: kandw %k1, %k0, %k0
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; CHECK-NEXT: kmovw %k0, %eax
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define i8 @select06(i8 %a.0, i8 %m) {
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%mask = bitcast i8 %m to <8 x i1>
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%a = bitcast i8 %a.0 to <8 x i1>
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%r = select <8 x i1> %mask, <8 x i1> %a, <8 x i1> zeroinitializer
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%res = bitcast <8 x i1> %r to i8
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ret i8 %res;
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}
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; CHECK-LABEL: select07
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; CHECK-DAG: kmovw %edx, %k0
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; CHECK-DAG: kmovw %edi, %k1
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; CHECK-DAG: kmovw %esi, %k2
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; CHECK: kandw %k0, %k1, %k1
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; CHECK-NEXT: knotw %k0, %k0
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; CHECK-NEXT: kandw %k0, %k2, %k0
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; CHECK-NEXT: korw %k0, %k1, %k0
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; CHECK-NEXT: kmovw %k0, %eax
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define i8 @select07(i8 %a.0, i8 %b.0, i8 %m) {
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%mask = bitcast i8 %m to <8 x i1>
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%a = bitcast i8 %a.0 to <8 x i1>
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%b = bitcast i8 %b.0 to <8 x i1>
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%r = select <8 x i1> %mask, <8 x i1> %a, <8 x i1> %b
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%res = bitcast <8 x i1> %r to i8
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ret i8 %res;
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}
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@ -14,8 +14,8 @@ target triple = "x86_64-apple-macosx"
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; <rdar://problem/18675020>
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; CHECK-LABEL: test:
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; CHECK: vmovdqa {{.*#+}} xmm0 = [65535,0,0,65535]
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; CHECK: vmovdqa {{.*#+}} xmm2 = [65533,124,125,14807]
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; CHECK: vmovdqa {{.*#+}} xmm1 = [65533,124,125,14807]
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; CHECK: vmovdqa {{.*#+}} xmm1 = [65535,0,0,65535]
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; CHECK: ret
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define void @test(<4 x i16>* %a, <4 x i16>* %b) {
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body:
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