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add the memri memory operand

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this makes it possible for ldr instructions with non-zero immediate


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29103 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2006-07-11 11:36:48 +00:00
parent 4a8aadd1f5
commit a4e64359aa
4 changed files with 41 additions and 13 deletions
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6
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -58,6 +58,12 @@ namespace {
return "ARM Assembly Printer";
}
void printMemRegImm(const MachineInstr *MI, unsigned OpNo) {
printOperand(MI, OpNo + 1);
O << ", ";
printOperand(MI, OpNo);
}
void printOperand(const MachineInstr *MI, int opNum);
void printMemOperand(const MachineInstr *MI, int opNum,
const char *Modifier = 0);

7
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@ -164,7 +164,7 @@ public:
void Select(SDOperand &Result, SDOperand Op);
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
bool SelectAddrReg(SDOperand N, SDOperand &Base);
bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base);
// Include the pieces autogenerated from the target description.
#include "ARMGenDAGISel.inc"
@ -183,7 +183,10 @@ void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
ScheduleAndEmitDAG(DAG);
}
bool ARMDAGToDAGISel::SelectAddrReg(SDOperand N, SDOperand &Base) {
//register plus/minus 12 bit offset
bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset,
SDOperand &Base) {
Offset = CurDAG->getTargetConstant(0, MVT::i32);
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
}

17
lib/Target/ARM/ARMInstrInfo.td
View File

@ -12,9 +12,18 @@
//
//===----------------------------------------------------------------------===//
// Address operands
def memri : Operand<iPTR> {
let PrintMethod = "printMemRegImm";
let NumMIOperands = 2;
let MIOperandInfo = (ops i32imm, ptr_rc);
}
// Define ARM specific addressing mode.
//register or frame index
def raddr : ComplexPattern<iPTR, 1, "SelectAddrReg", []>;
//register plus/minus 12 bit offset
def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", []>;
//register plus scaled register
//def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", []>;
//===----------------------------------------------------------------------===//
// Instructions
@ -42,9 +51,9 @@ def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
def bxr: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
def ldr : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
"ldr $dst, [$addr]",
[(set IntRegs:$dst, (load raddr:$addr))]>;
[(set IntRegs:$dst, (load iaddr:$addr))]>;
def str : InstARM<(ops IntRegs:$src, IntRegs:$addr),
"str $src, [$addr]",

24
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -83,23 +83,33 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
assert (MI.getOpcode() == ARM::ldr);
unsigned FrameIdx = 1;
unsigned FrameIdx = 2;
unsigned OffIdx = 1;
int FrameIndex = MI.getOperand(FrameIdx).getFrameIndex();
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
assert (MI.getOperand(OffIdx).getImmedValue() == 0);
unsigned StackSize = MF.getFrameInfo()->getStackSize();
Offset += StackSize;
// Insert a set of r12 with the full address
// r12 = r13 + offset
MachineBasicBlock *MBB2 = MI.getParent();
BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
assert (Offset >= 0);
if (Offset < 4096) {
// Replace the FrameIndex with r13
MI.getOperand(FrameIdx).ChangeToRegister(ARM::R13);
// Replace the ldr offset with Offset
MI.getOperand(OffIdx).ChangeToImmediate(Offset);
} else {
// Insert a set of r12 with the full address
// r12 = r13 + offset
MachineBasicBlock *MBB2 = MI.getParent();
BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
// Replace the FrameIndex with r12
MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12);
// Replace the FrameIndex with r12
MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12);
}
}
void ARMRegisterInfo::