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https://github.com/c64scene-ar/llvm-6502.git
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[FastISel][AArch64] Fix and extend the tbz/tbnz pattern matching.
The pattern matching failed to recognize all instances of "-1", because when comparing against "-1" we didn't use an APInt of the same bitwidth. This commit fixes this and also adds inverse versions of the conditon to catch more cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222722 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka
parent
e5aa5ce5b2
commit
a4ebd338c4
@ -2112,15 +2112,15 @@ bool AArch64FastISel::emitCompareAndBranch(const BranchInst *BI) {
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int TestBit = -1;
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bool IsCmpNE;
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if ((Predicate == CmpInst::ICMP_EQ) || (Predicate == CmpInst::ICMP_NE)) {
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if (const auto *C = dyn_cast<Constant>(LHS))
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if (C->isNullValue())
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std::swap(LHS, RHS);
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switch (Predicate) {
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default:
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return false;
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case CmpInst::ICMP_EQ:
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case CmpInst::ICMP_NE:
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if (isa<Constant>(LHS) && cast<Constant>(LHS)->isNullValue())
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std::swap(LHS, RHS);
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if (!isa<Constant>(RHS))
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return false;
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if (!cast<Constant>(RHS)->isNullValue())
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if (!isa<Constant>(RHS) || !cast<Constant>(RHS)->isNullValue())
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return false;
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if (const auto *AI = dyn_cast<BinaryOperator>(LHS))
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@ -2143,26 +2143,27 @@ bool AArch64FastISel::emitCompareAndBranch(const BranchInst *BI) {
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TestBit = 0;
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IsCmpNE = Predicate == CmpInst::ICMP_NE;
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} else if (Predicate == CmpInst::ICMP_SLT) {
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if (!isa<Constant>(RHS))
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return false;
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if (!cast<Constant>(RHS)->isNullValue())
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break;
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case CmpInst::ICMP_SLT:
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case CmpInst::ICMP_SGE:
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if (!isa<Constant>(RHS) || !cast<Constant>(RHS)->isNullValue())
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return false;
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TestBit = BW - 1;
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IsCmpNE = true;
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} else if (Predicate == CmpInst::ICMP_SGT) {
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IsCmpNE = Predicate == CmpInst::ICMP_SLT;
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break;
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case CmpInst::ICMP_SGT:
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case CmpInst::ICMP_SLE:
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if (!isa<ConstantInt>(RHS))
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return false;
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if (cast<ConstantInt>(RHS)->getValue() != -1)
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if (cast<ConstantInt>(RHS)->getValue() != APInt(BW, -1, true))
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return false;
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TestBit = BW - 1;
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IsCmpNE = false;
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} else
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return false;
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IsCmpNE = Predicate == CmpInst::ICMP_SLE;
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break;
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} // end switch
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static const unsigned OpcTable[2][2][2] = {
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{ {AArch64::CBZW, AArch64::CBZX },
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@ -1,5 +1,5 @@
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; RUN: llc -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s
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; RUN: llc -fast-isel -fast-isel-abort -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s
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; RUN: llc -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck --check-prefix=CHECK %s
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; RUN: llc -fast-isel -fast-isel-abort -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck --check-prefix=CHECK --check-prefix=FAST %s
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define i32 @icmp_eq_i8(i8 zeroext %a) {
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; CHECK-LABEL: icmp_eq_i8
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@ -121,6 +121,160 @@ bb2:
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ret i32 0
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}
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define i32 @icmp_slt_i8(i8 zeroext %a) {
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; FAST-LABEL: icmp_slt_i8
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; FAST: tbnz w0, #7, {{LBB.+_2}}
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%1 = icmp slt i8 %a, 0
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br i1 %1, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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define i32 @icmp_slt_i16(i16 zeroext %a) {
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; FAST-LABEL: icmp_slt_i16
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; FAST: tbnz w0, #15, {{LBB.+_2}}
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%1 = icmp slt i16 %a, 0
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br i1 %1, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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define i32 @icmp_slt_i32(i32 %a) {
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; CHECK-LABEL: icmp_slt_i32
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; CHECK: tbnz w0, #31, {{LBB.+_2}}
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%1 = icmp slt i32 %a, 0
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br i1 %1, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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define i32 @icmp_slt_i64(i64 %a) {
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; CHECK-LABEL: icmp_slt_i64
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; CHECK: tbnz x0, #63, {{LBB.+_2}}
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%1 = icmp slt i64 %a, 0
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br i1 %1, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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define i32 @icmp_sge_i8(i8 zeroext %a) {
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; FAST-LABEL: icmp_sge_i8
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; FAST: tbz w0, #7, {{LBB.+_2}}
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%1 = icmp sge i8 %a, 0
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br i1 %1, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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define i32 @icmp_sge_i16(i16 zeroext %a) {
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; FAST-LABEL: icmp_sge_i16
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; FAST: tbz w0, #15, {{LBB.+_2}}
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%1 = icmp sge i16 %a, 0
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br i1 %1, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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define i32 @icmp_sle_i8(i8 zeroext %a) {
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; FAST-LABEL: icmp_sle_i8
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; FAST: tbnz w0, #7, {{LBB.+_2}}
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%1 = icmp sle i8 %a, -1
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br i1 %1, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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define i32 @icmp_sle_i16(i16 zeroext %a) {
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; FAST-LABEL: icmp_sle_i16
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; FAST: tbnz w0, #15, {{LBB.+_2}}
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%1 = icmp sle i16 %a, -1
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br i1 %1, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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define i32 @icmp_sle_i32(i32 %a) {
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; CHECK-LABEL: icmp_sle_i32
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; CHECK: tbnz w0, #31, {{LBB.+_2}}
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%1 = icmp sle i32 %a, -1
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br i1 %1, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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define i32 @icmp_sle_i64(i64 %a) {
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; CHECK-LABEL: icmp_sle_i64
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; CHECK: tbnz x0, #63, {{LBB.+_2}}
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%1 = icmp sle i64 %a, -1
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br i1 %1, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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define i32 @icmp_sgt_i8(i8 zeroext %a) {
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; FAST-LABEL: icmp_sgt_i8
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; FAST: tbz w0, #7, {{LBB.+_2}}
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%1 = icmp sgt i8 %a, -1
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br i1 %1, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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define i32 @icmp_sgt_i16(i16 zeroext %a) {
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; FAST-LABEL: icmp_sgt_i16
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; FAST: tbz w0, #15, {{LBB.+_2}}
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%1 = icmp sgt i16 %a, -1
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br i1 %1, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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define i32 @icmp_sgt_i32(i32 %a) {
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; CHECK-LABEL: icmp_sgt_i32
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; CHECK: tbz w0, #31, {{LBB.+_2}}
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%1 = icmp sgt i32 %a, -1
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br i1 %1, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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define i32 @icmp_sgt_i64(i64 %a) {
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; FAST-LABEL: icmp_sgt_i64
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; FAST: tbz x0, #63, {{LBB.+_2}}
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%1 = icmp sgt i64 %a, -1
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br i1 %1, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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; Test that we don't fold the 'and' instruction into the compare.
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define i32 @icmp_eq_and_i32(i32 %a, i1 %c) {
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; CHECK-LABEL: icmp_eq_and_i32
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