6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-15 04:30:12 +00:00
Code Issues Projects Releases Wiki Activity

[Hexagon] Adding XTYPE/MPY intrinsic tests and some missing multiply instructions.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227347 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2015-01-28 19:16:17 +00:00
parent 61b9b31ef1
commit a5062b38a9
6 changed files with 1195 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -2273,6 +2273,7 @@ def M2_hmmpyl_rs1 : T_MType_rr2 <"mpy", 0b111, 0b100, 1, 1, ".l">;
// V4 Instructions
let isCodeGenOnly = 0 in {
def M2_mpysu_up : T_MType_rr1 <"mpysu", 0b011, 0b001, 0>;
def M2_mpy_up_s1 : T_MType_rr1 <"mpy", 0b101, 0b010, 0>;
def M2_mpy_up_s1_sat : T_MType_rr1 <"mpy", 0b111, 0b000, 1>;
def M2_hmmpyh_s1 : T_MType_rr2 <"mpy", 0b101, 0b000, 1, 0, ".h">;

13
lib/Target/Hexagon/HexagonInstrInfoV4.td
View File

@ -2123,10 +2123,6 @@ def : Pat <(add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
(i32 (M4_mpyrr_addi tglobaladdr:$src1, IntRegs:$src2,
IntRegs:$src3))>;
// Polynomial multiply words
// Rdd=pmpyw(Rs,Rt)
// Rxx^=pmpyw(Rs,Rt)
// Vector reduce multiply word by signed half (32x16)
// Rdd=vrmpyweh(Rss,Rtt)[:<<1]
// Rdd=vrmpywoh(Rss,Rtt)[:<<1]
@ -2152,6 +2148,15 @@ def : Pat <(add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
// Rdd=vpmpyh(Rs,Rt)
// Rxx^=vpmpyh(Rs,Rt)
// Polynomial multiply words
// Rdd=pmpyw(Rs,Rt)
let isCodeGenOnly = 0 in
def M4_pmpyw : T_XTYPE_mpy64 < "pmpyw", 0b010, 0b111, 0, 0, 0>;
// Rxx^=pmpyw(Rs,Rt)
let isCodeGenOnly = 0 in
def M4_pmpyw_acc : T_XTYPE_mpy64_acc < "pmpyw", "^", 0b001, 0b111, 0, 0, 0>;
//===----------------------------------------------------------------------===//
// XTYPE/MPY -
//===----------------------------------------------------------------------===//

8
lib/Target/Hexagon/HexagonIntrinsics.td
View File

@ -77,6 +77,14 @@ class T_IRI_pat <InstHexagon MI, Intrinsic IntID>
: Pat <(IntID imm:$It, I32:$Rs, imm:$Iu),
(MI imm:$It, I32:$Rs, imm:$Iu)>;
class T_IRR_pat <InstHexagon MI, Intrinsic IntID>
: Pat <(IntID imm:$Is, I32:$Rs, I32:$Rt),
(MI imm:$Is, I32:$Rs, I32:$Rt)>;
class T_RIR_pat <InstHexagon MI, Intrinsic IntID>
: Pat <(IntID I32:$Rs, imm:$Is, I32:$Rt),
(MI I32:$Rs, imm:$Is, I32:$Rt)>;
class T_RRR_pat <InstHexagon MI, Intrinsic IntID>
: Pat <(IntID I32:$Rs, I32:$Rt, I32:$Ru),
(MI I32:$Rs, I32:$Rt, I32:$Ru)>;

34
lib/Target/Hexagon/HexagonIntrinsicsV4.td
View File

@ -12,6 +12,28 @@
// 80-V9418-12 Rev. A
// June 15, 2010
// Polynomial multiply words
// Rdd=pmpyw(Rs,Rt)
def : T_RR_pat <M4_pmpyw, int_hexagon_M4_pmpyw>;
// Rxx^=pmpyw(Rs,Rt)
def : T_PRR_pat <M4_pmpyw_acc, int_hexagon_M4_pmpyw_acc>;
//Rxx^=asr(Rss,Rt)
def : T_PPR_pat <S2_asr_r_p_xor, int_hexagon_S2_asr_r_p_xor>;
//Rxx^=asl(Rss,Rt)
def : T_PPR_pat <S2_asl_r_p_xor, int_hexagon_S2_asl_r_p_xor>;
//Rxx^=lsr(Rss,Rt)
def : T_PPR_pat <S2_lsr_r_p_xor, int_hexagon_S2_lsr_r_p_xor>;
//Rxx^=lsl(Rss,Rt)
def : T_PPR_pat <S2_lsl_r_p_xor, int_hexagon_S2_lsl_r_p_xor>;
// Multiply and use upper result
def : MType_R32_pat <int_hexagon_M2_mpysu_up, M2_mpysu_up>;
def : MType_R32_pat <int_hexagon_M2_mpy_up_s1, M2_mpy_up_s1>;
def : MType_R32_pat <int_hexagon_M2_hmmpyh_s1, M2_hmmpyh_s1>;
def : MType_R32_pat <int_hexagon_M2_hmmpyl_s1, M2_hmmpyl_s1>;
def : MType_R32_pat <int_hexagon_M2_mpy_up_s1_sat, M2_mpy_up_s1_sat>;
def : T_P_pat <S2_brevp, int_hexagon_S2_brevp>;
def: T_P_pat <S2_ct0p, int_hexagon_S2_ct0p>;
@ -20,6 +42,18 @@ def: T_RR_pat<C4_nbitsset, int_hexagon_C4_nbitsset>;
def: T_RR_pat<C4_nbitsclr, int_hexagon_C4_nbitsclr>;
def: T_RI_pat<C4_nbitsclri, int_hexagon_C4_nbitsclri>;
def : Pat <(int_hexagon_M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2,
IntRegs:$src3),
(M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
def : T_IRR_pat <M4_mpyrr_addi, int_hexagon_M4_mpyrr_addi>;
def : T_IRI_pat <M4_mpyri_addi, int_hexagon_M4_mpyri_addi>;
def : T_RIR_pat <M4_mpyri_addr_u2, int_hexagon_M4_mpyri_addr_u2>;
def : T_RRI_pat <M4_mpyri_addr, int_hexagon_M4_mpyri_addr>;
// Multiply 32x32 and use upper result
def : T_RRR_pat <M4_mac_up_s1_sat, int_hexagon_M4_mac_up_s1_sat>;
def : T_RRR_pat <M4_nac_up_s1_sat, int_hexagon_M4_nac_up_s1_sat>;
// Extract bitfield
def : T_PP_pat <S4_extractp_rp, int_hexagon_S4_extractp_rp>;
def : T_RP_pat <S4_extract_rp, int_hexagon_S4_extract_rp>;

1135
test/CodeGen/Hexagon/intrinsics/xtype_mpy.ll Normal file
View File

File diff suppressed because it is too large Load Diff

10
test/MC/Disassembler/Hexagon/xtype_mpy.txt
View File

@ -166,6 +166,10 @@
# CHECK: r17 -= mpyu(r21.h, r31.l):<<1
0x71 0xdf 0xf5 0xee
# CHECK: r17 -= mpyu(r21.h, r31.h):<<1
0xf0 0xdf 0x55 0xe5
# CHECK: r17:16 = pmpyw(r21, r31)
0xf0 0xdf 0x35 0xe7
# CHECK: r17:16 ^= pmpyw(r21, r31)
0x31 0xdf 0x15 0xed
# CHECK: r17 = mpy(r21, r31)
0x31 0xdf 0x35 0xed
@ -178,12 +182,14 @@
# CHECK: r17 = mpy(r21, r31.h):<<1:sat
0x31 0xdf 0xb5 0xed
# CHECK: r17 = mpy(r21, r31.l):<<1:sat
0x11 0xdf 0xf5 0xed
# CHECK: r17 = mpy(r21, r31):<<1:sat
0x91 0xdf 0xb5 0xed
# CHECK: r17 = mpy(r21, r31.h):<<1:rnd:sat
0x11 0xdf 0xf5 0xed
# CHECK: r17 = mpy(r21, r31):<<1:sat
0x91 0xdf 0xf5 0xed
# CHECK: r17 = mpy(r21, r31.l):<<1:rnd:sat
0x51 0xdf 0xb5 0xed
# CHECK: r17 = mpy(r21, r31):<<1
0x11 0xdf 0x75 0xef
# CHECK: r17 += mpy(r21, r31):<<1:sat
0x31 0xdf 0x75 0xef