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rearrange some code to allow inferring instr info from the pattern of the instr, but don't do so yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45647 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -137,6 +137,40 @@ void InstrInfoEmitter::EmitOperandInfo(std::ostream &OS,
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}
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}
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//===----------------------------------------------------------------------===//
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// Instruction Analysis
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//===----------------------------------------------------------------------===//
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void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst,
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bool &isStore, bool &isLoad,
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bool &NeverHasSideEffects) {
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isStore = Inst.isStore;
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isLoad = Inst.isLoad;
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NeverHasSideEffects = Inst.neverHasSideEffects;
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const TreePattern *Pattern = CDP.getInstruction(Inst.TheDef).getPattern();
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if (Pattern == 0) return; // No pattern.
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// FIXME: Change this to use pattern info.
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if (dynamic_cast<ListInit*>(Inst.TheDef->getValueInit("Pattern"))) {
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ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
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if (LI && LI->getSize() > 0) {
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DagInit *Dag = (DagInit *)LI->getElement(0);
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DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
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if (OpDef) {
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Record *Operator = OpDef->getDef();
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if (Operator->isSubClassOf("SDNode")) {
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const std::string Opcode = Operator->getValueAsString("Opcode");
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if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE")
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isStore = true;
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}
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}
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}
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}
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}
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//===----------------------------------------------------------------------===//
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// Main Output.
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//===----------------------------------------------------------------------===//
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@ -196,43 +230,27 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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std::map<std::vector<Record*>, unsigned> &EmittedLists,
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const OperandInfoMapTy &OpInfo,
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std::ostream &OS) {
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int MinOperands;
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// Determine properties of the instruction from its pattern.
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bool isStore, isLoad, NeverHasSideEffects;
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InferFromPattern(Inst, isStore, isLoad, NeverHasSideEffects);
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if (NeverHasSideEffects && Inst.mayHaveSideEffects) {
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std::cerr << "error: Instruction '" << Inst.getName()
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<< "' is marked with 'mayHaveSideEffects', but it can never have them!\n";
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exit(1);
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}
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int MinOperands = 0;
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if (!Inst.OperandList.empty())
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// Each logical operand can be multiple MI operands.
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MinOperands = Inst.OperandList.back().MIOperandNo +
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Inst.OperandList.back().MINumOperands;
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else
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MinOperands = 0;
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OS << " { ";
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OS << Num << ",\t" << MinOperands << ",\t"
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<< Inst.NumDefs << ",\t\"";
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if (Inst.Name.empty())
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OS << Inst.TheDef->getName();
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else
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OS << Inst.Name;
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<< Inst.NumDefs << ",\t\"" << Inst.getName();
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OS << "\",\t" << getItinClassNumber(Inst.TheDef) << ", 0";
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// Try to determine (from the pattern), if the instruction is a store.
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bool isStore = false;
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if (dynamic_cast<ListInit*>(Inst.TheDef->getValueInit("Pattern"))) {
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ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
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if (LI && LI->getSize() > 0) {
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DagInit *Dag = (DagInit *)LI->getElement(0);
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DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
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if (OpDef) {
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Record *Operator = OpDef->getDef();
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if (Operator->isSubClassOf("SDNode")) {
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const std::string Opcode = Operator->getValueAsString("Opcode");
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if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE")
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isStore = true;
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}
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}
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}
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}
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// Emit all of the target indepedent flags...
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if (Inst.isReturn) OS << "|M_RET_FLAG";
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if (Inst.isBranch) OS << "|M_BRANCH_FLAG";
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@ -240,21 +258,21 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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if (Inst.isBarrier) OS << "|M_BARRIER_FLAG";
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if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
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if (Inst.isCall) OS << "|M_CALL_FLAG";
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if (Inst.isLoad) OS << "|M_LOAD_FLAG";
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if (Inst.isStore || isStore) OS << "|M_STORE_FLAG";
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if (isLoad) OS << "|M_LOAD_FLAG";
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if (isStore) OS << "|M_STORE_FLAG";
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if (Inst.isImplicitDef)OS << "|M_IMPLICIT_DEF_FLAG";
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if (Inst.isPredicable) OS << "|M_PREDICABLE";
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if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
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if (Inst.isCommutable) OS << "|M_COMMUTABLE";
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if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
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if (Inst.isReMaterializable) OS << "|M_REMATERIALIZIBLE";
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if (Inst.isNotDuplicable) OS << "|M_NOT_DUPLICABLE";
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if (Inst.hasOptionalDef) OS << "|M_HAS_OPTIONAL_DEF";
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if (Inst.isNotDuplicable) OS << "|M_NOT_DUPLICABLE";
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if (Inst.hasOptionalDef) OS << "|M_HAS_OPTIONAL_DEF";
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if (Inst.usesCustomDAGSchedInserter)
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OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
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if (Inst.hasVariableNumberOfOperands) OS << "|M_VARIABLE_OPS";
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if (Inst.mayHaveSideEffects) OS << "|M_MAY_HAVE_SIDE_EFFECTS";
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if (Inst.neverHasSideEffects) OS << "|M_NEVER_HAS_SIDE_EFFECTS";
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if (Inst.mayHaveSideEffects) OS << "|M_MAY_HAVE_SIDE_EFFECTS";
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if (NeverHasSideEffects) OS << "|M_NEVER_HAS_SIDE_EFFECTS";
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OS << ", 0";
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// Emit all of the target-specific flags...
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@ -41,6 +41,10 @@ public:
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private:
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typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
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// Instruction analysis.
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void InferFromPattern(const CodeGenInstruction &Inst,
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bool &isStore, bool &isLoad, bool &NeverHasSideEffects);
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void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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Record *InstrInfo,
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std::map<std::vector<Record*>, unsigned> &EL,
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