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Fix single word and unsigned byte data transfer instruction encodings so that

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Inst{4} = 0.

rdar://problem/9213022


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128662 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-03-31 19:28:35 +00:00
parent a6f7499244
commit a52d7da1d8
2 changed files with 6 additions and 0 deletions
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2
lib/Target/ARM/ARMInstrInfo.td
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@ -991,6 +991,7 @@ multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
[(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
bits<4> Rt; bits<4> Rt;
bits<17> shift; bits<17> shift;
let shift{4} = 0; // Inst{4} = 0
let Inst{23} = shift{12}; // U (add = ('U' == 1)) let Inst{23} = shift{12}; // U (add = ('U' == 1))
let Inst{19-16} = shift{16-13}; // Rn let Inst{19-16} = shift{16-13}; // Rn
let Inst{15-12} = Rt; let Inst{15-12} = Rt;
@ -1020,6 +1021,7 @@ multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
[(opnode GPR:$Rt, ldst_so_reg:$shift)]> { [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
bits<4> Rt; bits<4> Rt;
bits<17> shift; bits<17> shift;
let shift{4} = 0; // Inst{4} = 0
let Inst{23} = shift{12}; // U (add = ('U' == 1)) let Inst{23} = shift{12}; // U (add = ('U' == 1))
let Inst{19-16} = shift{16-13}; // Rn let Inst{19-16} = shift{16-13}; // Rn
let Inst{15-12} = Rt; let Inst{15-12} = Rt;

4
test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt Normal file
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@ -0,0 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# LDR (register) has encoding Inst{4} = 0.
0xba 0xae 0x9f 0x57