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ARM add missing Thumb1 two-operand aliases for shift-by-immediate.
rdar://11222742 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154457 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1407,3 +1407,11 @@ def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
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def : tInstAlias<"neg${s}${p} $Rd, $Rm",
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(tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;
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// Implied destination operand forms for shifts.
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def : tInstAlias<"lsl${s}${p} $Rdm, $imm",
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(tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>;
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def : tInstAlias<"lsr${s}${p} $Rdm, $imm",
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(tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
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def : tInstAlias<"asr${s}${p} $Rdm, $imm",
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(tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
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@ -6650,6 +6650,37 @@ processInstruction(MCInst &Inst,
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return true;
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}
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// Handle encoding choice for the shift-immediate instructions.
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case ARM::t2LSLri:
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case ARM::t2LSRri:
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case ARM::t2ASRri: {
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if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
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Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
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Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
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!(static_cast<ARMOperand*>(Operands[3])->isToken() &&
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static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
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unsigned NewOpc;
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switch (Inst.getOpcode()) {
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default: llvm_unreachable("unexpected opcode");
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case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
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case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
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case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
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}
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// The Thumb1 operands aren't in the same order. Awesome, eh?
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MCInst TmpInst;
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TmpInst.setOpcode(NewOpc);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(5));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(Inst.getOperand(2));
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TmpInst.addOperand(Inst.getOperand(3));
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TmpInst.addOperand(Inst.getOperand(4));
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Inst = TmpInst;
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return true;
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}
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return false;
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}
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// Handle the Thumb2 mode MOV complex aliases.
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case ARM::t2MOVsr:
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case ARM::t2MOVSsr: {
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@ -97,10 +97,16 @@ _func:
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asrs r2, r3, #32
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asrs r2, r3, #5
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asrs r2, r3, #1
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asrs r5, #21
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asrs r5, r5, #21
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asrs r3, r5, #21
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@ CHECK: asrs r2, r3, #32 @ encoding: [0x1a,0x10]
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@ CHECK: asrs r2, r3, #5 @ encoding: [0x5a,0x11]
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@ CHECK: asrs r2, r3, #1 @ encoding: [0x5a,0x10]
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@ CHECK: asrs r5, r5, #21 @ encoding: [0x6d,0x15]
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@ CHECK: asrs r5, r5, #21 @ encoding: [0x6d,0x15]
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@ CHECK: asrs r3, r5, #21 @ encoding: [0x6b,0x15]
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@------------------------------------------------------------------------------
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@ -319,9 +325,15 @@ _func:
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@------------------------------------------------------------------------------
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lsls r4, r5, #0
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lsls r4, r5, #4
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lsls r3, #12
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lsls r3, r3, #12
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lsls r1, r3, #12
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@ CHECK: lsls r4, r5, #0 @ encoding: [0x2c,0x00]
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@ CHECK: lsls r4, r5, #4 @ encoding: [0x2c,0x01]
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@ CHECK: lsls r3, r3, #12 @ encoding: [0x1b,0x03]
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@ CHECK: lsls r3, r3, #12 @ encoding: [0x1b,0x03]
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@ CHECK: lsls r1, r3, #12 @ encoding: [0x19,0x03]
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@------------------------------------------------------------------------------
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@ -337,9 +349,15 @@ _func:
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@------------------------------------------------------------------------------
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lsrs r1, r3, #1
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lsrs r1, r3, #32
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lsrs r4, #20
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lsrs r4, r4, #20
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lsrs r2, r4, #20
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@ CHECK: lsrs r1, r3, #1 @ encoding: [0x59,0x08]
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@ CHECK: lsrs r1, r3, #32 @ encoding: [0x19,0x08]
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@ CHECK: lsrs r4, r4, #20 @ encoding: [0x24,0x0d]
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@ CHECK: lsrs r4, r4, #20 @ encoding: [0x24,0x0d]
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@ CHECK: lsrs r2, r4, #20 @ encoding: [0x22,0x0d]
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@------------------------------------------------------------------------------
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