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Implemented aarch64 Neon scalar vmulx_lane intrinsics
Implemented aarch64 Neon scalar vfma_lane intrinsics Implemented aarch64 Neon scalar vfms_lane intrinsics Implemented legacy vmul_n_f64, vmul_lane_f64, vmul_laneq_f64 intrinsics (v1f64 parameter type) using Neon scalar instructions. Implemented legacy vfma_lane_f64, vfms_lane_f64, vfma_laneq_f64, vfms_laneq_f64 intrinsics (v1f64 parameter type) using Neon scalar instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194888 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ana Pazos
parent
6bc810a499
commit
a53bf06f7a
@ -67,8 +67,9 @@ def int_aarch64_neon_vpmaxnm : Neon_2Arg_Intrinsic;
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// Vector Pairwise minNum (Floating Point)
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def int_aarch64_neon_vpminnm : Neon_2Arg_Intrinsic;
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// Vector Multiply Extended (Floating Point)
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def int_aarch64_neon_vmulx : Neon_2Arg_Intrinsic;
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// Vector Multiply Extended and Scalar Multiply Extended (Floating Point)
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def int_aarch64_neon_vmulx :
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Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>;
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class Neon_N2V_Intrinsic
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: Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, llvm_i32_ty],
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@ -3653,6 +3653,8 @@ defm ST1WB4V_1D : NeonI_STWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
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// End of post-index vector load/store multiple N-element structure
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// (class SIMD lselem-post)
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// Neon Scalar instructions implementation
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// Scalar Three Same
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class NeonI_Scalar3Same_size<bit u, bits<2> size, bits<5> opcode, string asmop,
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@ -4360,8 +4362,17 @@ defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrsqrts, FRSQRTSsss,
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// Patterns to match llvm.aarch64.* intrinsic for
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// Scalar Floating-point Multiply Extended,
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defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vmulx, FMULXsss,
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FMULXddd>;
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multiclass Neon_Scalar3Same_MULX_SD_size_patterns<SDPatternOperator opnode,
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Instruction INSTS,
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Instruction INSTD> {
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def : Pat<(f32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
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(INSTS FPR32:$Rn, FPR32:$Rm)>;
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def : Pat<(f64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
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(INSTD FPR64:$Rn, FPR64:$Rm)>;
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}
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defm : Neon_Scalar3Same_MULX_SD_size_patterns<int_aarch64_neon_vmulx,
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FMULXsss,FMULXddd>;
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// Scalar Integer Shift Left (Signed, Unsigned)
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def SSHLddd : NeonI_Scalar3Same_D_size<0b0, 0b01000, "sshl">;
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@ -4794,6 +4805,51 @@ def FMULXddv_2D : NeonI_ScalarXIndexedElemArith<"fmulx",
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let Inst{20-16} = MRm;
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}
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multiclass Neon_ScalarXIndexedElem_MUL_MULX_Patterns<
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SDPatternOperator opnode,
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Instruction INST,
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ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
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ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
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def : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
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(ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)))),
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(ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
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def : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
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(ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)))),
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(ResTy (INST (ResTy FPRC:$Rn),
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(ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
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OpNImm:$Imm))>;
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// swapped operands
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def : Pat<(ResTy (opnode
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(ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
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(ResTy FPRC:$Rn))),
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(ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
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def : Pat<(ResTy (opnode
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(ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
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(ResTy FPRC:$Rn))),
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(ResTy (INST (ResTy FPRC:$Rn),
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(ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
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OpNImm:$Imm))>;
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}
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// Patterns for Scalar Floating Point multiply (scalar, by element)
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defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULssv_4S,
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f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
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defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULddv_2D,
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f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
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// Patterns for Scalar Floating Point multiply extended (scalar, by element)
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defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
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FMULXssv_4S, f32, FPR32, v4f32, neon_uimm2_bare,
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v2f32, v4f32, neon_uimm1_bare>;
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defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
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FMULXddv_2D, f64, FPR64, v2f64, neon_uimm1_bare,
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v1f64, v2f64, neon_uimm0_bare>;
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// Scalar Floating Point fused multiply-add (scalar, by element)
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def FMLAssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
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0b0001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
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@ -4821,6 +4877,83 @@ def FMLSddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
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let Inst{21} = 0b0; // l
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let Inst{20-16} = MRm;
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}
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// We are allowed to match the fma instruction regardless of compile options.
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multiclass Neon_ScalarXIndexedElem_FMA_Patterns<
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Instruction FMLAI, Instruction FMLSI,
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ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
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ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
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// fmla
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def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
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(ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
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(ResTy FPRC:$Ra))),
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(ResTy (FMLAI (ResTy FPRC:$Ra),
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(ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
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def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
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(ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
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(ResTy FPRC:$Ra))),
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(ResTy (FMLAI (ResTy FPRC:$Ra),
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(ResTy FPRC:$Rn),
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(ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
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OpNImm:$Imm))>;
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// swapped fmla operands
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def : Pat<(ResTy (fma
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(ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
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(ResTy FPRC:$Rn),
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(ResTy FPRC:$Ra))),
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(ResTy (FMLAI (ResTy FPRC:$Ra),
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(ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
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def : Pat<(ResTy (fma
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(ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
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(ResTy FPRC:$Rn),
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(ResTy FPRC:$Ra))),
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(ResTy (FMLAI (ResTy FPRC:$Ra),
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(ResTy FPRC:$Rn),
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(ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
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OpNImm:$Imm))>;
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// fmls
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def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
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(fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
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(ResTy FPRC:$Ra))),
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(ResTy (FMLSI (ResTy FPRC:$Ra),
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(ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
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def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
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(fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
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(ResTy FPRC:$Ra))),
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(ResTy (FMLSI (ResTy FPRC:$Ra),
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(ResTy FPRC:$Rn),
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(ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
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OpNImm:$Imm))>;
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// swapped fmls operands
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def : Pat<(ResTy (fma
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(fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
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(ResTy FPRC:$Rn),
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(ResTy FPRC:$Ra))),
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(ResTy (FMLSI (ResTy FPRC:$Ra),
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(ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
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def : Pat<(ResTy (fma
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(fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
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(ResTy FPRC:$Rn),
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(ResTy FPRC:$Ra))),
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(ResTy (FMLSI (ResTy FPRC:$Ra),
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(ResTy FPRC:$Rn),
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(ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
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OpNImm:$Imm))>;
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}
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// Scalar Floating Point fused multiply-add and multiply-subtract (scalar, by element)
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defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAssv_4S, FMLSssv_4S,
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f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
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defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
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f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
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defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
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f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
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// Scalar Signed saturating doubling multiply-add long (scalar, by element)
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def SQDMLALshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
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@ -4990,6 +5123,40 @@ def DUPdv_D : NeonI_Scalar_DUP<"dup", "d", FPR64, VPR128, neon_uimm1_bare> {
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let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
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}
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multiclass NeonI_Scalar_DUP_Elt_pattern<Instruction DUPI, ValueType ResTy,
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ValueType OpTy, Operand OpImm,
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ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
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def : Pat<(ResTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
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(ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
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def : Pat<(ResTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
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(ResTy (DUPI
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(ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
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OpNImm:$Imm))>;
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}
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// Patterns for vector extract of FP data using scalar DUP instructions
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defm : NeonI_Scalar_DUP_Elt_pattern<DUPsv_S, f32,
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v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
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defm : NeonI_Scalar_DUP_Elt_pattern<DUPdv_D, f64,
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v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
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multiclass NeonI_Scalar_DUP_alias<string asmop, string asmlane,
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Instruction DUPI, Operand OpImm,
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RegisterClass ResRC> {
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def : NeonInstAlias<!strconcat(asmop, "$Rd, $Rn." # asmlane # "[$Imm]"),
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(DUPI ResRC:$Rd, VPR128:$Rn, OpImm:$Imm), 0b0>;
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}
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// Aliases for Scalar copy - DUP element (scalar)
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// FIXME: This is actually the preferred syntax but TableGen can't deal with
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// custom printing of aliases.
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defm : NeonI_Scalar_DUP_alias<"mov", ".b", DUPbv_B, neon_uimm4_bare, FPR8>;
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defm : NeonI_Scalar_DUP_alias<"mov", ".h", DUPhv_H, neon_uimm3_bare, FPR16>;
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defm : NeonI_Scalar_DUP_alias<"mov", ".s", DUPsv_S, neon_uimm2_bare, FPR32>;
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defm : NeonI_Scalar_DUP_alias<"mov", ".d", DUPdv_D, neon_uimm1_bare, FPR64>;
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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108
test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
Normal file
108
test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
Normal file
@ -0,0 +1,108 @@
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
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declare float @llvm.fma.f32(float, float, float)
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declare double @llvm.fma.f64(double, double, double)
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define float @test_fmla_ss4S(float %a, float %b, <4 x float> %v) {
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; CHECK: test_fmla_ss4S
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; CHECK: fmla {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-31]+}}.s[3]
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%tmp1 = extractelement <4 x float> %v, i32 3
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%tmp2 = call float @llvm.fma.f32(float %b, float %tmp1, float %a)
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ret float %tmp2
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}
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define float @test_fmla_ss4S_swap(float %a, float %b, <4 x float> %v) {
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; CHECK: test_fmla_ss4S_swap
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; CHECK: fmla {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-31]+}}.s[3]
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%tmp1 = extractelement <4 x float> %v, i32 3
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%tmp2 = call float @llvm.fma.f32(float %tmp1, float %a, float %a)
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ret float %tmp2
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}
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define float @test_fmla_ss2S(float %a, float %b, <2 x float> %v) {
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; CHECK: test_fmla_ss2S
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; CHECK: fmla {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-31]+}}.s[1]
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%tmp1 = extractelement <2 x float> %v, i32 1
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%tmp2 = call float @llvm.fma.f32(float %b, float %tmp1, float %a)
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ret float %tmp2
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}
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define double @test_fmla_ddD(double %a, double %b, <1 x double> %v) {
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; CHECK: test_fmla_ddD
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; CHECK: fmla {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-31]+}}.d[0]
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%tmp1 = extractelement <1 x double> %v, i32 0
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%tmp2 = call double @llvm.fma.f64(double %b, double %tmp1, double %a)
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ret double %tmp2
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}
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define double @test_fmla_dd2D(double %a, double %b, <2 x double> %v) {
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; CHECK: test_fmla_dd2D
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; CHECK: fmla {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-31]+}}.d[1]
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%tmp1 = extractelement <2 x double> %v, i32 1
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%tmp2 = call double @llvm.fma.f64(double %b, double %tmp1, double %a)
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ret double %tmp2
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}
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define double @test_fmla_dd2D_swap(double %a, double %b, <2 x double> %v) {
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; CHECK: test_fmla_dd2D_swap
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; CHECK: fmla {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-31]+}}.d[1]
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%tmp1 = extractelement <2 x double> %v, i32 1
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%tmp2 = call double @llvm.fma.f64(double %tmp1, double %b, double %a)
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ret double %tmp2
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}
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define float @test_fmls_ss4S(float %a, float %b, <4 x float> %v) {
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; CHECK: test_fmls_ss4S
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; CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-31]+}}.s[3]
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%tmp1 = extractelement <4 x float> %v, i32 3
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%tmp2 = fsub float -0.0, %tmp1
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%tmp3 = call float @llvm.fma.f32(float %tmp2, float %tmp1, float %a)
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ret float %tmp3
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}
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define float @test_fmls_ss4S_swap(float %a, float %b, <4 x float> %v) {
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; CHECK: test_fmls_ss4S_swap
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; CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-31]+}}.s[3]
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%tmp1 = extractelement <4 x float> %v, i32 3
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%tmp2 = fsub float -0.0, %tmp1
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%tmp3 = call float @llvm.fma.f32(float %tmp1, float %tmp2, float %a)
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ret float %tmp3
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}
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define float @test_fmls_ss2S(float %a, float %b, <2 x float> %v) {
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; CHECK: test_fmls_ss2S
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; CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-31]+}}.s[1]
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%tmp1 = extractelement <2 x float> %v, i32 1
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%tmp2 = fsub float -0.0, %tmp1
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%tmp3 = call float @llvm.fma.f32(float %tmp2, float %tmp1, float %a)
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ret float %tmp3
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}
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define double @test_fmls_ddD(double %a, double %b, <1 x double> %v) {
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; CHECK: test_fmls_ddD
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; CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-31]+}}.d[0]
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%tmp1 = extractelement <1 x double> %v, i32 0
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%tmp2 = fsub double -0.0, %tmp1
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%tmp3 = call double @llvm.fma.f64(double %tmp2, double %tmp1, double %a)
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ret double %tmp3
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}
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define double @test_fmls_dd2D(double %a, double %b, <2 x double> %v) {
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; CHECK: test_fmls_dd2D
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; CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-31]+}}.d[1]
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%tmp1 = extractelement <2 x double> %v, i32 1
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%tmp2 = fsub double -0.0, %tmp1
|
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%tmp3 = call double @llvm.fma.f64(double %tmp2, double %tmp1, double %a)
|
||||
ret double %tmp3
|
||||
}
|
||||
|
||||
define double @test_fmls_dd2D_swap(double %a, double %b, <2 x double> %v) {
|
||||
; CHECK: test_fmls_dd2D_swap
|
||||
; CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-31]+}}.d[1]
|
||||
%tmp1 = extractelement <2 x double> %v, i32 1
|
||||
%tmp2 = fsub double -0.0, %tmp1
|
||||
%tmp3 = call double @llvm.fma.f64(double %tmp1, double %tmp2, double %a)
|
||||
ret double %tmp3
|
||||
}
|
||||
|
||||
124
test/CodeGen/AArch64/neon-scalar-by-elem-mul.ll
Normal file
124
test/CodeGen/AArch64/neon-scalar-by-elem-mul.ll
Normal file
@ -0,0 +1,124 @@
|
||||
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
|
||||
|
||||
define float @test_fmul_lane_ss2S(float %a, <2 x float> %v) {
|
||||
; CHECK: test_fmul_lane_ss2S
|
||||
; CHECK: fmul {{s[0-31]+}}, {{s[0-31]+}}, {{v[0-31]+}}.s[1]
|
||||
%tmp1 = extractelement <2 x float> %v, i32 1
|
||||
%tmp2 = fmul float %a, %tmp1;
|
||||
ret float %tmp2;
|
||||
}
|
||||
|
||||
define float @test_fmul_lane_ss2S_swap(float %a, <2 x float> %v) {
|
||||
; CHECK: test_fmul_lane_ss2S_swap
|
||||
; CHECK: fmul {{s[0-31]+}}, {{s[0-31]+}}, {{v[0-31]+}}.s[1]
|
||||
%tmp1 = extractelement <2 x float> %v, i32 1
|
||||
%tmp2 = fmul float %tmp1, %a;
|
||||
ret float %tmp2;
|
||||
}
|
||||
|
||||
|
||||
define float @test_fmul_lane_ss4S(float %a, <4 x float> %v) {
|
||||
; CHECK: test_fmul_lane_ss4S
|
||||
; CHECK: fmul {{s[0-31]+}}, {{s[0-31]+}}, {{v[0-31]+}}.s[3]
|
||||
%tmp1 = extractelement <4 x float> %v, i32 3
|
||||
%tmp2 = fmul float %a, %tmp1;
|
||||
ret float %tmp2;
|
||||
}
|
||||
|
||||
define float @test_fmul_lane_ss4S_swap(float %a, <4 x float> %v) {
|
||||
; CHECK: test_fmul_lane_ss4S_swap
|
||||
; CHECK: fmul {{s[0-31]+}}, {{s[0-31]+}}, {{v[0-31]+}}.s[3]
|
||||
%tmp1 = extractelement <4 x float> %v, i32 3
|
||||
%tmp2 = fmul float %tmp1, %a;
|
||||
ret float %tmp2;
|
||||
}
|
||||
|
||||
|
||||
define double @test_fmul_lane_ddD(double %a, <1 x double> %v) {
|
||||
; CHECK: test_fmul_lane_ddD
|
||||
; CHECK: fmul {{d[0-31]+}}, {{d[0-31]+}}, {{v[0-31]+}}.d[0]
|
||||
%tmp1 = extractelement <1 x double> %v, i32 0
|
||||
%tmp2 = fmul double %a, %tmp1;
|
||||
ret double %tmp2;
|
||||
}
|
||||
|
||||
|
||||
|
||||
define double @test_fmul_lane_dd2D(double %a, <2 x double> %v) {
|
||||
; CHECK: test_fmul_lane_dd2D
|
||||
; CHECK: fmul {{d[0-31]+}}, {{d[0-31]+}}, {{v[0-31]+}}.d[1]
|
||||
%tmp1 = extractelement <2 x double> %v, i32 1
|
||||
%tmp2 = fmul double %a, %tmp1;
|
||||
ret double %tmp2;
|
||||
}
|
||||
|
||||
|
||||
define double @test_fmul_lane_dd2D_swap(double %a, <2 x double> %v) {
|
||||
; CHECK: test_fmul_lane_dd2D_swap
|
||||
; CHECK: fmul {{d[0-31]+}}, {{d[0-31]+}}, {{v[0-31]+}}.d[1]
|
||||
%tmp1 = extractelement <2 x double> %v, i32 1
|
||||
%tmp2 = fmul double %tmp1, %a;
|
||||
ret double %tmp2;
|
||||
}
|
||||
|
||||
declare float @llvm.aarch64.neon.vmulx.f32(float, float)
|
||||
|
||||
define float @test_fmulx_lane_f32(float %a, <2 x float> %v) {
|
||||
; CHECK: test_fmulx_lane_f32
|
||||
; CHECK: fmulx {{s[0-31]+}}, {{s[0-31]+}}, {{v[0-31]+}}.s[1]
|
||||
%tmp1 = extractelement <2 x float> %v, i32 1
|
||||
%tmp2 = call float @llvm.aarch64.neon.vmulx.f32(float %a, float %tmp1)
|
||||
ret float %tmp2;
|
||||
}
|
||||
|
||||
define float @test_fmulx_laneq_f32(float %a, <4 x float> %v) {
|
||||
; CHECK: test_fmulx_laneq_f32
|
||||
; CHECK: fmulx {{s[0-31]+}}, {{s[0-31]+}}, {{v[0-31]+}}.s[3]
|
||||
%tmp1 = extractelement <4 x float> %v, i32 3
|
||||
%tmp2 = call float @llvm.aarch64.neon.vmulx.f32(float %a, float %tmp1)
|
||||
ret float %tmp2;
|
||||
}
|
||||
|
||||
define float @test_fmulx_laneq_f32_swap(float %a, <4 x float> %v) {
|
||||
; CHECK: test_fmulx_laneq_f32_swap
|
||||
; CHECK: fmulx {{s[0-31]+}}, {{s[0-31]+}}, {{v[0-31]+}}.s[3]
|
||||
%tmp1 = extractelement <4 x float> %v, i32 3
|
||||
%tmp2 = call float @llvm.aarch64.neon.vmulx.f32(float %tmp1, float %a)
|
||||
ret float %tmp2;
|
||||
}
|
||||
|
||||
declare double @llvm.aarch64.neon.vmulx.f64(double, double)
|
||||
|
||||
define double @test_fmulx_lane_f64(double %a, <1 x double> %v) {
|
||||
; CHECK: test_fmulx_lane_f64
|
||||
; CHECK: fmulx {{d[0-31]+}}, {{d[0-31]+}}, {{v[0-31]+}}.d[0]
|
||||
%tmp1 = extractelement <1 x double> %v, i32 0
|
||||
%tmp2 = call double @llvm.aarch64.neon.vmulx.f64(double %a, double %tmp1)
|
||||
ret double %tmp2;
|
||||
}
|
||||
|
||||
define double @test_fmulx_laneq_f64_0(double %a, <2 x double> %v) {
|
||||
; CHECK: test_fmulx_laneq_f64_0
|
||||
; CHECK: fmulx {{d[0-31]+}}, {{d[0-31]+}}, {{v[0-31]+}}.d[0]
|
||||
%tmp1 = extractelement <2 x double> %v, i32 0
|
||||
%tmp2 = call double @llvm.aarch64.neon.vmulx.f64(double %a, double %tmp1)
|
||||
ret double %tmp2;
|
||||
}
|
||||
|
||||
|
||||
define double @test_fmulx_laneq_f64_1(double %a, <2 x double> %v) {
|
||||
; CHECK: test_fmulx_laneq_f64_1
|
||||
; CHECK: fmulx {{d[0-31]+}}, {{d[0-31]+}}, {{v[0-31]+}}.d[1]
|
||||
%tmp1 = extractelement <2 x double> %v, i32 1
|
||||
%tmp2 = call double @llvm.aarch64.neon.vmulx.f64(double %a, double %tmp1)
|
||||
ret double %tmp2;
|
||||
}
|
||||
|
||||
define double @test_fmulx_laneq_f64_1_swap(double %a, <2 x double> %v) {
|
||||
; CHECK: test_fmulx_laneq_f64_1_swap
|
||||
; CHECK: fmulx {{d[0-31]+}}, {{d[0-31]+}}, {{v[0-31]+}}.d[1]
|
||||
%tmp1 = extractelement <2 x double> %v, i32 1
|
||||
%tmp2 = call double @llvm.aarch64.neon.vmulx.f64(double %tmp1, double %a)
|
||||
ret double %tmp2;
|
||||
}
|
||||
|
||||
@ -49,25 +49,19 @@ declare <1 x i32> @llvm.arm.neon.vqrdmulh.v1i32(<1 x i32>, <1 x i32>)
|
||||
define float @test_vmulxs_f32(float %a, float %b) {
|
||||
; CHECK: test_vmulxs_f32
|
||||
; CHECK: fmulx {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
||||
%1 = insertelement <1 x float> undef, float %a, i32 0
|
||||
%2 = insertelement <1 x float> undef, float %b, i32 0
|
||||
%3 = call <1 x float> @llvm.aarch64.neon.vmulx.v1f32(<1 x float> %1, <1 x float> %2)
|
||||
%4 = extractelement <1 x float> %3, i32 0
|
||||
ret float %4
|
||||
%1 = call float @llvm.aarch64.neon.vmulx.f32(float %a, float %b)
|
||||
ret float %1
|
||||
}
|
||||
|
||||
define double @test_vmulxd_f64(double %a, double %b) {
|
||||
; CHECK: test_vmulxd_f64
|
||||
; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
|
||||
%1 = insertelement <1 x double> undef, double %a, i32 0
|
||||
%2 = insertelement <1 x double> undef, double %b, i32 0
|
||||
%3 = call <1 x double> @llvm.aarch64.neon.vmulx.v1f64(<1 x double> %1, <1 x double> %2)
|
||||
%4 = extractelement <1 x double> %3, i32 0
|
||||
ret double %4
|
||||
%1 = call double @llvm.aarch64.neon.vmulx.f64(double %a, double %b)
|
||||
ret double %1
|
||||
}
|
||||
|
||||
declare <1 x float> @llvm.aarch64.neon.vmulx.v1f32(<1 x float>, <1 x float>)
|
||||
declare <1 x double> @llvm.aarch64.neon.vmulx.v1f64(<1 x double>, <1 x double>)
|
||||
declare float @llvm.aarch64.neon.vmulx.f32(float, float)
|
||||
declare double @llvm.aarch64.neon.vmulx.f64(double, double)
|
||||
|
||||
define i32 @test_vqdmlalh_s16(i32 %a, i16 %b, i16 %c) {
|
||||
; CHECK: test_vqdmlalh_s16
|
||||
|
||||
Loading…
Reference in New Issue
Block a user