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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
Improve systemz to model cmp and ucmp nodes as returning
their flags correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99738 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -316,19 +316,19 @@ def FBCONVF64 : Pseudo<(outs FP64:$dst), (ins GR64:$src),
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let Defs = [PSW] in {
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let Defs = [PSW] in {
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def FCMP32rr : Pseudo<(outs), (ins FP32:$src1, FP32:$src2),
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def FCMP32rr : Pseudo<(outs), (ins FP32:$src1, FP32:$src2),
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"cebr\t$src1, $src2",
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"cebr\t$src1, $src2",
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[(SystemZcmp FP32:$src1, FP32:$src2), (implicit PSW)]>;
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[(set PSW, (SystemZcmp FP32:$src1, FP32:$src2))]>;
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def FCMP64rr : Pseudo<(outs), (ins FP64:$src1, FP64:$src2),
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def FCMP64rr : Pseudo<(outs), (ins FP64:$src1, FP64:$src2),
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"cdbr\t$src1, $src2",
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"cdbr\t$src1, $src2",
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[(SystemZcmp FP64:$src1, FP64:$src2), (implicit PSW)]>;
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[(set PSW, (SystemZcmp FP64:$src1, FP64:$src2))]>;
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def FCMP32rm : Pseudo<(outs), (ins FP32:$src1, rriaddr12:$src2),
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def FCMP32rm : Pseudo<(outs), (ins FP32:$src1, rriaddr12:$src2),
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"ceb\t$src1, $src2",
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"ceb\t$src1, $src2",
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[(SystemZcmp FP32:$src1, (load rriaddr12:$src2)),
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[(set PSW, (SystemZcmp FP32:$src1,
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(implicit PSW)]>;
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(load rriaddr12:$src2)))]>;
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def FCMP64rm : Pseudo<(outs), (ins FP64:$src1, rriaddr12:$src2),
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def FCMP64rm : Pseudo<(outs), (ins FP64:$src1, rriaddr12:$src2),
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"cdb\t$src1, $src2",
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"cdb\t$src1, $src2",
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[(SystemZcmp FP64:$src1, (load rriaddr12:$src2)),
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[(set PSW, (SystemZcmp FP64:$src1,
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(implicit PSW)]>;
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(load rriaddr12:$src2)))]>;
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} // Defs = [PSW]
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} // Defs = [PSW]
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -31,7 +31,8 @@ class SDTCisI64<int OpNum> : SDTCisVT<OpNum, i64>;
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def SDT_SystemZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
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def SDT_SystemZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
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def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>;
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def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>;
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def SDT_SystemZCallSeqEnd : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>;
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def SDT_SystemZCallSeqEnd : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>;
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def SDT_CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
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def SDT_CmpTest : SDTypeProfile<1, 2, [SDTCisI64<0>,
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SDTCisSameAs<1, 2>]>;
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def SDT_BrCond : SDTypeProfile<0, 3,
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def SDT_BrCond : SDTypeProfile<0, 3,
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[SDTCisVT<0, OtherVT>,
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[SDTCisVT<0, OtherVT>,
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SDTCisI8<1>, SDTCisVT<2, i64>]>;
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SDTCisI8<1>, SDTCisVT<2, i64>]>;
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@ -980,100 +981,89 @@ let Defs = [PSW] in {
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def CMP32rr : RRI<0x19,
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def CMP32rr : RRI<0x19,
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(outs), (ins GR32:$src1, GR32:$src2),
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(outs), (ins GR32:$src1, GR32:$src2),
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"cr\t$src1, $src2",
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"cr\t$src1, $src2",
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[(SystemZcmp GR32:$src1, GR32:$src2),
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[(set PSW, (SystemZcmp GR32:$src1, GR32:$src2))]>;
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(implicit PSW)]>;
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def CMP64rr : RREI<0xB920,
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def CMP64rr : RREI<0xB920,
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(outs), (ins GR64:$src1, GR64:$src2),
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(outs), (ins GR64:$src1, GR64:$src2),
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"cgr\t$src1, $src2",
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"cgr\t$src1, $src2",
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[(SystemZcmp GR64:$src1, GR64:$src2),
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[(set PSW, (SystemZcmp GR64:$src1, GR64:$src2))]>;
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(implicit PSW)]>;
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def CMP32ri : RILI<0xC2D,
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def CMP32ri : RILI<0xC2D,
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(outs), (ins GR32:$src1, s32imm:$src2),
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(outs), (ins GR32:$src1, s32imm:$src2),
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"cfi\t$src1, $src2",
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"cfi\t$src1, $src2",
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[(SystemZcmp GR32:$src1, imm:$src2),
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[(set PSW, (SystemZcmp GR32:$src1, imm:$src2))]>;
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(implicit PSW)]>;
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def CMP64ri32 : RILI<0xC2C,
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def CMP64ri32 : RILI<0xC2C,
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(outs), (ins GR64:$src1, s32imm64:$src2),
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(outs), (ins GR64:$src1, s32imm64:$src2),
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"cgfi\t$src1, $src2",
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"cgfi\t$src1, $src2",
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[(SystemZcmp GR64:$src1, i64immSExt32:$src2),
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[(set PSW, (SystemZcmp GR64:$src1, i64immSExt32:$src2))]>;
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(implicit PSW)]>;
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def CMP32rm : RXI<0x59,
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def CMP32rm : RXI<0x59,
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(outs), (ins GR32:$src1, rriaddr12:$src2),
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(outs), (ins GR32:$src1, rriaddr12:$src2),
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"c\t$src1, $src2",
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"c\t$src1, $src2",
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[(SystemZcmp GR32:$src1, (load rriaddr12:$src2)),
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[(set PSW, (SystemZcmp GR32:$src1, (load rriaddr12:$src2)))]>;
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(implicit PSW)]>;
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def CMP32rmy : RXYI<0xE359,
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def CMP32rmy : RXYI<0xE359,
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(outs), (ins GR32:$src1, rriaddr:$src2),
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(outs), (ins GR32:$src1, rriaddr:$src2),
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"cy\t$src1, $src2",
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"cy\t$src1, $src2",
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[(SystemZcmp GR32:$src1, (load rriaddr:$src2)),
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[(set PSW, (SystemZcmp GR32:$src1, (load rriaddr:$src2)))]>;
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(implicit PSW)]>;
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def CMP64rm : RXYI<0xE320,
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def CMP64rm : RXYI<0xE320,
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(outs), (ins GR64:$src1, rriaddr:$src2),
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(outs), (ins GR64:$src1, rriaddr:$src2),
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"cg\t$src1, $src2",
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"cg\t$src1, $src2",
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[(SystemZcmp GR64:$src1, (load rriaddr:$src2)),
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[(set PSW, (SystemZcmp GR64:$src1, (load rriaddr:$src2)))]>;
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(implicit PSW)]>;
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def UCMP32rr : RRI<0x15,
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def UCMP32rr : RRI<0x15,
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(outs), (ins GR32:$src1, GR32:$src2),
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(outs), (ins GR32:$src1, GR32:$src2),
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"clr\t$src1, $src2",
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"clr\t$src1, $src2",
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[(SystemZucmp GR32:$src1, GR32:$src2),
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[(set PSW, (SystemZucmp GR32:$src1, GR32:$src2))]>;
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(implicit PSW)]>;
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def UCMP64rr : RREI<0xB921,
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def UCMP64rr : RREI<0xB921,
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(outs), (ins GR64:$src1, GR64:$src2),
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(outs), (ins GR64:$src1, GR64:$src2),
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"clgr\t$src1, $src2",
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"clgr\t$src1, $src2",
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[(SystemZucmp GR64:$src1, GR64:$src2),
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[(set PSW, (SystemZucmp GR64:$src1, GR64:$src2))]>;
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(implicit PSW)]>;
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def UCMP32ri : RILI<0xC2F,
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def UCMP32ri : RILI<0xC2F,
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(outs), (ins GR32:$src1, i32imm:$src2),
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(outs), (ins GR32:$src1, i32imm:$src2),
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"clfi\t$src1, $src2",
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"clfi\t$src1, $src2",
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[(SystemZucmp GR32:$src1, imm:$src2),
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[(set PSW, (SystemZucmp GR32:$src1, imm:$src2))]>;
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(implicit PSW)]>;
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def UCMP64ri32 : RILI<0xC2E,
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def UCMP64ri32 : RILI<0xC2E,
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(outs), (ins GR64:$src1, i64i32imm:$src2),
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(outs), (ins GR64:$src1, i64i32imm:$src2),
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"clgfi\t$src1, $src2",
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"clgfi\t$src1, $src2",
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[(SystemZucmp GR64:$src1, i64immZExt32:$src2),
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[(set PSW,(SystemZucmp GR64:$src1, i64immZExt32:$src2))]>;
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(implicit PSW)]>;
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def UCMP32rm : RXI<0x55,
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def UCMP32rm : RXI<0x55,
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(outs), (ins GR32:$src1, rriaddr12:$src2),
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(outs), (ins GR32:$src1, rriaddr12:$src2),
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"cl\t$src1, $src2",
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"cl\t$src1, $src2",
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[(SystemZucmp GR32:$src1, (load rriaddr12:$src2)),
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[(set PSW, (SystemZucmp GR32:$src1,
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(implicit PSW)]>;
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(load rriaddr12:$src2)))]>;
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def UCMP32rmy : RXYI<0xE355,
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def UCMP32rmy : RXYI<0xE355,
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(outs), (ins GR32:$src1, rriaddr:$src2),
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(outs), (ins GR32:$src1, rriaddr:$src2),
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"cly\t$src1, $src2",
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"cly\t$src1, $src2",
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[(SystemZucmp GR32:$src1, (load rriaddr:$src2)),
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[(set PSW, (SystemZucmp GR32:$src1,
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(implicit PSW)]>;
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(load rriaddr:$src2)))]>;
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def UCMP64rm : RXYI<0xE351,
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def UCMP64rm : RXYI<0xE351,
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(outs), (ins GR64:$src1, rriaddr:$src2),
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(outs), (ins GR64:$src1, rriaddr:$src2),
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"clg\t$src1, $src2",
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"clg\t$src1, $src2",
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[(SystemZucmp GR64:$src1, (load rriaddr:$src2)),
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[(set PSW, (SystemZucmp GR64:$src1,
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(implicit PSW)]>;
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(load rriaddr:$src2)))]>;
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def CMPSX64rr32 : RREI<0xB930,
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def CMPSX64rr32 : RREI<0xB930,
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(outs), (ins GR64:$src1, GR32:$src2),
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(outs), (ins GR64:$src1, GR32:$src2),
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"cgfr\t$src1, $src2",
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"cgfr\t$src1, $src2",
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[(SystemZucmp GR64:$src1, (sext GR32:$src2)),
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[(set PSW, (SystemZucmp GR64:$src1,
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(implicit PSW)]>;
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(sext GR32:$src2)))]>;
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def UCMPZX64rr32 : RREI<0xB931,
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def UCMPZX64rr32 : RREI<0xB931,
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(outs), (ins GR64:$src1, GR32:$src2),
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(outs), (ins GR64:$src1, GR32:$src2),
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"clgfr\t$src1, $src2",
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"clgfr\t$src1, $src2",
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[(SystemZucmp GR64:$src1, (zext GR32:$src2)),
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[(set PSW, (SystemZucmp GR64:$src1,
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(implicit PSW)]>;
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(zext GR32:$src2)))]>;
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def CMPSX64rm32 : RXYI<0xE330,
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def CMPSX64rm32 : RXYI<0xE330,
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(outs), (ins GR64:$src1, rriaddr:$src2),
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(outs), (ins GR64:$src1, rriaddr:$src2),
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"cgf\t$src1, $src2",
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"cgf\t$src1, $src2",
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[(SystemZucmp GR64:$src1, (sextloadi64i32 rriaddr:$src2)),
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[(set PSW, (SystemZucmp GR64:$src1,
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(implicit PSW)]>;
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(sextloadi64i32 rriaddr:$src2)))]>;
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def UCMPZX64rm32 : RXYI<0xE331,
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def UCMPZX64rm32 : RXYI<0xE331,
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(outs), (ins GR64:$src1, rriaddr:$src2),
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(outs), (ins GR64:$src1, rriaddr:$src2),
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"clgf\t$src1, $src2",
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"clgf\t$src1, $src2",
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[(SystemZucmp GR64:$src1, (zextloadi64i32 rriaddr:$src2)),
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[(set PSW, (SystemZucmp GR64:$src1,
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(implicit PSW)]>;
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(zextloadi64i32 rriaddr:$src2)))]>;
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// FIXME: Add other crazy ucmp forms
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// FIXME: Add other crazy ucmp forms
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