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Reorder some parts of the td file to by in alphabetical order

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165590 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler 2012-10-10 01:58:16 +00:00
parent 3c9019d08f
commit a5971e8c00
1 changed files with 76 additions and 65 deletions
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141
lib/Target/Mips/Mips16InstrInfo.td
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@ -11,69 +11,19 @@
//
//===----------------------------------------------------------------------===//
//
// This are pseudo formats for multiply
// This first one can be changed to non pseudo now.
//fmul
class FMULT16_ins<string asmstr, InstrItinClass itin> :
MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
!strconcat(asmstr, "\t$rx, $ry"), []>;
class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
!strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
let isCodeGenOnly=1;
}
//
// RRR-type instruction format
//
class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
!strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
//
// I8_MOVR32 instruction format (used only by the MOVR32 instructio
//
class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32),
!strconcat(asmstr, "\t$rz, $r32"), [], itin>;
//
// I8_MOV32R instruction format (used only by MOV32R instruction)
//
class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz),
!strconcat(asmstr, "\t$r32, $rz"), [], itin>;
//
// RR-type instruction format
//
class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
!strconcat(asmstr, "\t$rx, $ry"), [], itin> {
}
class FRR16_M_ins<bits<5> f, string asmstr,
InstrItinClass itin> :
FRR16<f, (outs CPU16Regs:$rx), (ins),
!strconcat(asmstr, "\t$rx"), [], itin>;
class FRxRxRy16_ins<bits<5> f, string asmstr,
InstrItinClass itin> :
FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
!strconcat(asmstr, "\t$rz, $ry"),
[], itin> {
let Constraints = "$rx = $rz";
// Address operand
def mem16 : Operand<i32> {
let PrintMethod = "printMemOperand";
let MIOperandInfo = (ops CPU16Regs, simm16);
let EncoderMethod = "getMemEncoding";
}
let rx=0 in
class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
string asmstr, InstrItinClass itin>:
FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
[], itin> ;
//
// Assembler formats in alphabetical order.
// Natural and pseudos are mixed together.
//
//
// EXT-RI instruction format
//
@ -90,7 +40,6 @@ class FEXT_RI16_ins<bits<5> _op, string asmstr,
class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
class FEXT_2RI16_ins<bits<5> _op, string asmstr,
InstrItinClass itin>:
FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
@ -126,14 +75,76 @@ class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa),
!strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
//
// Address operand
def mem16 : Operand<i32> {
let PrintMethod = "printMemOperand";
let MIOperandInfo = (ops CPU16Regs, simm16);
let EncoderMethod = "getMemEncoding";
// I8_MOVR32 instruction format (used only by the MOVR32 instructio
//
class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32),
!strconcat(asmstr, "\t$rz, $r32"), [], itin>;
//
// I8_MOV32R instruction format (used only by MOV32R instruction)
//
class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz),
!strconcat(asmstr, "\t$r32, $rz"), [], itin>;
//
// This are pseudo formats for multiply
// This first one can be changed to non pseudo now.
//
// MULT
//
class FMULT16_ins<string asmstr, InstrItinClass itin> :
MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
!strconcat(asmstr, "\t$rx, $ry"), []>;
//
// MULT-LO
//
class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
!strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
let isCodeGenOnly=1;
}
//
// RR-type instruction format
//
class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
!strconcat(asmstr, "\t$rx, $ry"), [], itin> {
}
class FRR16_M_ins<bits<5> f, string asmstr,
InstrItinClass itin> :
FRR16<f, (outs CPU16Regs:$rx), (ins),
!strconcat(asmstr, "\t$rx"), [], itin>;
class FRxRxRy16_ins<bits<5> f, string asmstr,
InstrItinClass itin> :
FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
!strconcat(asmstr, "\t$rz, $ry"),
[], itin> {
let Constraints = "$rx = $rz";
}
let rx=0 in
class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
string asmstr, InstrItinClass itin>:
FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
[], itin> ;
//
// RRR-type instruction format
//
class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
!strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
//
// Some general instruction class info
//