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Reorder some parts of the td file to by in alphabetical order
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165590 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -11,69 +11,19 @@
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//
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//===----------------------------------------------------------------------===//
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//
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// This are pseudo formats for multiply
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// This first one can be changed to non pseudo now.
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//fmul
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class FMULT16_ins<string asmstr, InstrItinClass itin> :
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MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry"), []>;
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class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
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MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
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let isCodeGenOnly=1;
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}
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//
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// RRR-type instruction format
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//
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class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
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FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
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//
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// I8_MOVR32 instruction format (used only by the MOVR32 instructio
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//
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class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
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FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32),
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!strconcat(asmstr, "\t$rz, $r32"), [], itin>;
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//
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// I8_MOV32R instruction format (used only by MOV32R instruction)
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//
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class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
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FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz),
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!strconcat(asmstr, "\t$r32, $rz"), [], itin>;
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//
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// RR-type instruction format
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//
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class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
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FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry"), [], itin> {
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}
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class FRR16_M_ins<bits<5> f, string asmstr,
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InstrItinClass itin> :
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FRR16<f, (outs CPU16Regs:$rx), (ins),
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!strconcat(asmstr, "\t$rx"), [], itin>;
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class FRxRxRy16_ins<bits<5> f, string asmstr,
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InstrItinClass itin> :
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FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rz, $ry"),
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[], itin> {
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let Constraints = "$rx = $rz";
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// Address operand
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def mem16 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops CPU16Regs, simm16);
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let EncoderMethod = "getMemEncoding";
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}
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let rx=0 in
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class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
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string asmstr, InstrItinClass itin>:
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FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
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[], itin> ;
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//
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// Assembler formats in alphabetical order.
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// Natural and pseudos are mixed together.
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//
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//
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// EXT-RI instruction format
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//
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@ -90,7 +40,6 @@ class FEXT_RI16_ins<bits<5> _op, string asmstr,
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class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
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FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
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class FEXT_2RI16_ins<bits<5> _op, string asmstr,
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InstrItinClass itin>:
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FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
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@ -126,14 +75,76 @@ class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
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FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa),
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!strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
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//
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// Address operand
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def mem16 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops CPU16Regs, simm16);
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let EncoderMethod = "getMemEncoding";
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// I8_MOVR32 instruction format (used only by the MOVR32 instructio
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//
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class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
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FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32),
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!strconcat(asmstr, "\t$rz, $r32"), [], itin>;
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//
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// I8_MOV32R instruction format (used only by MOV32R instruction)
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//
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class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
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FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz),
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!strconcat(asmstr, "\t$r32, $rz"), [], itin>;
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//
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// This are pseudo formats for multiply
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// This first one can be changed to non pseudo now.
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//
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// MULT
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//
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class FMULT16_ins<string asmstr, InstrItinClass itin> :
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MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry"), []>;
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//
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// MULT-LO
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//
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class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
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MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
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let isCodeGenOnly=1;
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}
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//
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// RR-type instruction format
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//
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class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
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FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry"), [], itin> {
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}
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class FRR16_M_ins<bits<5> f, string asmstr,
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InstrItinClass itin> :
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FRR16<f, (outs CPU16Regs:$rx), (ins),
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!strconcat(asmstr, "\t$rx"), [], itin>;
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class FRxRxRy16_ins<bits<5> f, string asmstr,
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InstrItinClass itin> :
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FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rz, $ry"),
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[], itin> {
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let Constraints = "$rx = $rz";
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}
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let rx=0 in
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class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
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string asmstr, InstrItinClass itin>:
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FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
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[], itin> ;
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//
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// RRR-type instruction format
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//
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class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
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FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
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//
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// Some general instruction class info
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//
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