In asm's, output operands with matching input constraints

have to be registers, per gcc documentation.  This affects
the logic for determining what "g" should lower to.  PR 7393.
A couple of existing testcases are affected.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107079 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen 2010-06-28 22:09:45 +00:00
parent f187ac5a23
commit a5989f8e22
4 changed files with 21 additions and 5 deletions

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@ -2570,6 +2570,11 @@ static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
} }
} }
// Things with matching constraints can only be registers, per gcc
// documentation. This mainly affects "g" constraints.
if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
continue;
// This constraint letter is more general than the previous one, use it. // This constraint letter is more general than the previous one, use it.
int Generality = getConstraintGenerality(CType); int Generality = getConstraintGenerality(CType);
if (Generality > BestGenerality) { if (Generality > BestGenerality) {

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@ -1,5 +1,5 @@
; RUN: llc < %s -march=x86 | grep "#%ebp %esi %edi 8(%edx) %eax (%ebx)" ; RUN: llc < %s -march=x86 | grep "#%ebp %edi %ebx 8(%esi) %eax %dl"
; RUN: llc < %s -march=x86 -regalloc=fast | grep "#%edi %ebx %edx 8(%ebp) %eax (%esi)" ; RUN: llc < %s -march=x86 -regalloc=fast | grep "#%ebx %esi %edi 8(%ebp) %eax %dl"
; The 1st, 2nd, 3rd and 5th registers above must all be different. The registers ; The 1st, 2nd, 3rd and 5th registers above must all be different. The registers
; referenced in the 4th and 6th operands must not be the same as the 1st or 5th ; referenced in the 4th and 6th operands must not be the same as the 1st or 5th

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@ -0,0 +1,11 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin11 | FileCheck %s
; Any register is OK for %0, but it must be a register, not memory.
define i32 @foo() nounwind ssp {
entry:
; CHECK: GCROOT %eax
%_r = alloca i32, align 4 ; <i32*> [#uses=2]
call void asm "/* GCROOT $0 */", "=*imr,0,~{dirflag},~{fpsr},~{flags}"(i32* %_r, i32 4) nounwind
%0 = load i32* %_r, align 4 ; <i32> [#uses=1]
ret i32 %0
}

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@ -12,5 +12,5 @@ void avg_pixels8_mmx2(uint8_t *block, const uint8_t *pixels, int line_size, int
:"+g"(h), "+S"(pixels), "+D"(block) :"+g"(h), "+S"(pixels), "+D"(block)
:"r" ((x86_reg)line_size) :"r" ((x86_reg)line_size)
:"%""rax", "memory"); :"%""rax", "memory");
// CHECK: # (%rsp) %rsi %rdi %rcx // CHECK: # %ecx %rsi %rdi %rdx
} }